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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: wanna_bmw who wrote (162408)	3/17/2002 9:47:54 PM
From: Elmer	Respond to of 186894

While you are correct that this will make routing easier and more compact, it will also mean more steps in manufacturing, which mean longer turn-around times, and more $$$. I just don't know whether the pros outweigh the cons. At 7 metal layers... EP

To: wanna_bmw who wrote (162408)	3/17/2002 9:54:26 PM
From: Paul Engel	Read Replies (1) \| Respond to of 186894

Beamer - Re: ", but I've been under the impression that extra metal layers are a liability, rather than an asset. AMD's .13u process has 9 copper layers. While you are correct that this will make routing easier and more compact, it will also mean more steps in manufacturing, which mean longer turn-around times, and more $$$. I just don't know whether the pros outweigh the cons" You have identified the trade-offs - smaller die sizes vs added manufacturing complexity and cost. With 1 extra metal layer, I'd guess their are 3 extra mask steps out of about 25 or so mask steps. Roughly, that will cost an extra 3/25 or 12%. If the die size can be reduced by at LEAST 12%, it is a wash. For die size reduction >12%, the smaller die size wins, assuming no loss in yields. For Intel, this is a GOOD trade off - for AMD, with their poor 34% yields at 6 metal layers, adding 3 more layers is going to be a nightmare. Paul

To: wanna_bmw who wrote (162408)	3/18/2002 12:53:55 AM
From: maui_dude	Read Replies (1) \| Respond to of 186894

bmw, Re : "I've been under the impression that extra metal layers are a liability, rather than an asset." Designs could certainly absorb one or two extra layer every new process. Intel has 1 extra layer for 0.09 and that would help their design teams a lot. (BTW, I find it impossible to believe that AMD got 3 additional layers on their .09 process - somebody must be counting poly as a routing layer). At smaller processes like 0.09, the shielding of signals becomes critical (due to cross-check problems). You start needing additional layer just to keep your logic of larger processes functional (like routing to repeaters, decoupling capacitors, etc). At .13 and lower, interconnect is a big limitor (not devices) and the more the metal layer available the merrier to help improve die size, functionality and productivity. My guess is that the cost for 1 additional layer is insignificant compared to the gains from it. Maui.