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To: fyodor_ who wrote (75067)3/20/2002 4:49:15 PM
From: Dan3Read Replies (2) | Respond to of 275872
 
Looks like sharing a memory bus, which is what Itanic and Xeon do, puts something of a cramp on scaleability.

Fortunately, Hammer's architecture has a better way (multiple connections to memory when more processors are added).

AS WE REPORTED earlier, Intel was showing some McKinley results at its big big stand at CeBIT 2002.
See Intel McKinley benchmarks shown at CeBIT....

One processor completed the test in 19.18 seconds, two processors in 9.71 seconds, four processors in 9.57 seconds.
theinquirer.net



To: fyodor_ who wrote (75067)3/20/2002 5:41:06 PM
From: AK2004Respond to of 275872
 
fyodor
thanks, I read it in some short note (I'll try to locate) that via is ahead of schedule with their kt400.
Would t-bred support ddr400?
Regards
-Albert


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