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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?


To: Yousef who wrote (75566)3/25/2002 10:27:28 PM
From: ElmerRead Replies (2) | Respond to of 275872
 
Defect density MATTERS !!!

You know this goes right over their heads don't you? If they were smart enough to understand this they would have figured out the line of sh*t Jerry is feeding them.

EP



To: Yousef who wrote (75566)3/25/2002 10:58:09 PM
From: pgerassiRead Replies (2) | Respond to of 275872
 
Dear Yousef:

You forgot the most valuable point! The smaller die at the same defect density has a much higher yield. In other words, big is bad!

Defect density does not vary that much between cutting edge fabs at similar times as the wafers supplied to each fab come from the same sources (and any big differences would cause a shift in suppliers so they have great incentives to deliver product with not much larger defect densities than competitors). And most of those defects are caused by the underlying wafer are they not? Thus, the highest variable in these equations in typical use is the die size. And that does not favor Intel.

Pete



To: Yousef who wrote (75566)3/25/2002 11:00:11 PM
From: Dan3Read Replies (2) | Respond to of 275872
 
Re: Here are the two most commonly used equations for calculating yield from defect density and die size

That's very helpful, Yousef. We already have the die sizes.

Now be a nice fellow and post the defect densities of Intel and AMD's leading processes so we can plug in the numbers.

Thanking you in advance,

Dan



To: Yousef who wrote (75566)3/26/2002 12:38:51 AM
From: hmalyRead Replies (1) | Respond to of 275872
 
Yousef Re...Yield = [[1 - e^-AD]/AD]^2 ... A = chip area in cm^2 ... D = defect density in defects/cm^2<<<<<

Thanks for the post. I have a couple of questions. From previous discussions, I had assumed "defect density" meant the number of defects expected in a area of silicon before processing, which would of itself destroy a chip. Your formula for BE also includes a multiplier of n for the number of layers, but the MUR formula doesn't. Why? What determines defect density. The no. of bad chips, or the defects one can expect in silicon? If the defect density is compiled by totaling bad die/cm^2, are all processing errors called defect densities.



To: Yousef who wrote (75566)3/26/2002 12:50:48 AM
From: milo_moraiRead Replies (1) | Respond to of 275872
 
I'm surprised that you posted something that is quantifiable.

Why does only one of the formula's include layers?

Seems you're missing some important data.

Now is AMD still stuck at 300Mhz? #reply-13723463



To: Yousef who wrote (75566)3/26/2002 1:14:51 AM
From: AK2004Read Replies (1) | Respond to of 275872
 
Yousef
re: (Albert ... Please pay attention <ggg>)
I do , I do, If you don't mind I'll move it to Intel thread <ggggggg>