SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?


To: Yousef who wrote (75663)3/26/2002 9:26:02 PM
From: AK2004Respond to of 275872
 
Yosef
re: my assignment
Message 17248647
so what was my assignment again, professor?



To: Yousef who wrote (75663)3/27/2002 12:22:16 PM
From: pgerassiRead Replies (1) | Respond to of 275872
 
Dear Yousef:

At some point diminishing returns occurs. Putting caches on the memory chips was tried and found to be highly effective. As more memory was added the caches got larger naturally. Of course adding 256kb cache to a 256Mb DRAM die is trivial in terms of die area. But with a system having 8GB of memory (256 chips), the total cache would be 8MB which is much larger than current desktop CPU dies have. At the Hammer limit of 1TB, the cache would total 1GB far larger than any single die could hold. And best of all, no CPU die changes are required. Small systems have small caches and large systems have big caches. Of course this would be L3 cache and it would have huge bandwidth to main memory and huge bandwidth to Hammer since its spread over many channels.

You must be a one track technology mind. There are many ways to solve these problems, not just the one you or Intel happens to favor. You and they have been wrong before and will again. This is just one of those times.

Pete