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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: AK2004 who wrote (75672)	3/26/2002 10:37:37 PM
From: Dan3	Read Replies (2) \| Respond to of 275872

Spotted on the web... I don't remember seeing this before. It is certainly wrong about the debut date, but maybe it's right about the debut speed.... or maybe it's wrong about that too. Thoroughbred at Comdex Fall 2001 ◦ Die Size : 80mm(e.g Palomino : 129mm) ◦ Process : 0.13 micron ◦ L2 Cache : 256KB **Unless L2 cache has no improvement of performance, it could be shown as more higher speed. ◦ Initial Clock : M24001+(1.93Ghz:expected) ◦ Debut : 2002 2/4 extendpc.com

To: AK2004 who wrote (75672)	3/27/2002 1:06:08 AM
From: Ali Chen	Read Replies (2) \| Respond to of 275872

Albert, "amd expects to quadruple an output in that time frame." I think output is not the point. The point is that AMD tactics to match performance of Intel's offerings plays always at financial disadvantage. Being second-best in reality (or perception, does not matter) always dictates depressed ASP, which, in the long run, translates into less resources to compete, and makes their life miserable. We have seen this global trend over the whole AMD history, unfortunately. "I do hope that hammer performance boost would be sufficient to last that long." I do hope too, but my believes are shaken. How exactly the Hammer family is going to improve performance? As I said, inner IPCs are saturated for the x86 ISA. Small hope is that 16 registers would improve both inner IPC and reduce off-chip traffic, but I do not expect much, especially when AMD has no control over industrial compilers. The other big hope is the on-chip memory controller. First, people need to realize that it reduces only latency, the bandwidth remains the same. So let's assume a typical task completion budget for a 1.6GHz CPU, say 33% CPU ("inner IPC"), 33% memory bandwidth, and 33% latency. If you look at recent data for the EV7 (21364)with embedded RAMBUS controller, they claim the best load-to-use latency of 75ns. That's all they can do, and Alpha people are not dumb at all. I do not know the exact data for DDR Athlon latency, but for P-III/133 it is currently about 100ns, a commonly cited number. If we generously assume that the Hammer latency will be cut in half, it gives us only 16% improvement. For inner IPC I would not expect more than 20%, so it is 7% only, for a total of 23%. This is maximum, under additional assumption that application binaries are recompiled with proper compiler, which will not happen overnight. On the other side, Intel also has few resources available, immediately: hyperthreading (software is all ready), and 133/533 FSB, which improves both latency and bandwidth (assuming proper memory). This alone will nullify the Hammer memory advantages. Suffuce to say that nothing prevents Intel from incorporating the memory controller on-chip too. So, what again? Sounds like performance parity again, at best. With all ASP consequences and financial suffering. To firmly establish itself on Wall-Street, AMD needs a performance-killing platform, not some nit-picking optimizations of few extra dies per wafer. AMD has had that chance with Athlon, but someone at AMD blew it. (who would it be <ggg>?) They could employ a 133-MHz bus from the very beginning, and make a kill. Instead, there was an idiotic opinion among the highest AMD officials that they have "better bus". You know what? The EV6 bus was designed for Alpha 21264, with 2-4-8MB caches in mind, so the traffic was expected to be next to zero. No wonder that performance of the bus took a serious hit when paired with a miserable 256kB cache. In short, in previous post I tried to outline the strategic problem with AMD, taking into account global trends, not current performance kludges and tactics. In replies, most people are talking about insignificant short-term details. Regards, - Ali