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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Ali Chen who wrote (75688)	3/27/2002 2:08:51 AM
From: AK2004	Read Replies (1) \| Respond to of 275872

Ali re: I think output is not the point. I was going along with your logic that is large cache. If amd is not planning to quadruple output then why would they need that much of a capacity. With 7.5B in capex last year it was pretty clear that Intel is not taking any chances. AMD was pretty clear about building up capcity to match intel's, at least in virtual sense. :-)) AMD was less clear about capacity use though. re: If you look at recent data for the EV7 (21364)with embedded RAMBUS controller, they claim the best load-to-use latency of 75ns. That's all they can do, and Alpha people are not dumb at all......The EV6 bus was designed for Alpha 21264, with 2-4-8MB caches in mind, maybe that is all that they needed, just a guess. re: To firmly establish itself on Wall-Street, AMD needs a performance-killing platform, not some nit-picking optimizations of few extra dies per wafer after alpha Streat cares very little for killer platforms. Compatability and predictability even at lower cost is the key. It is expected by the Street that Intel would have higher margins and it is already priced in. re: In replies, most people are talking about insignificant short-term details. true but in defence I can say that short term is all we know with any degree of accuracy. As I mentioned before it is very possible that sometime by the end of '05 hammer family would be on it's way out. And we do not know what would follow but judging by capacity build-up k9 should have high transistor count. Regards -Albert

To: Ali Chen who wrote (75688)	3/27/2002 12:39:25 PM
From: pgerassi	Read Replies (1) \| Respond to of 275872

Dear Ali: Current DDRDRAM has a latency of 5 cycles 1 for command, 2 for RAS and 2 for CAS. It transfers a cache line of 64 bytes in 8 data xfers or 4 cycles. Thus latency is larger than bandwidth and that is when the memory is directly connected. Add a cycle for FSB arbitration and a cycle for NB switching and syncronization and you have 7 cycles of latency and 4 cycles of data transfer. Thus a cache line fill takes 11 cycles where bandwidth states it takes only 4 cycles to actually move the data. So the ratio is not 1/3 but more like 50 cycles for CPU per cache line fill, 112 cycles for latency and 64 cycles for bandwidth. Bandwidth only is 64/226 or 28%. Latency is 112/226 or about 50%. Cutting latency in half increases performance by 56/170 or 33%. Doubling bandwidth only raises performance by 32/194 or 17%. Reducing latency has a higher beta to performance. Going to a 133MHZ QDR FSB for P4 reduces latency by 5 to 10 cycles and this has the higher effect than the bandwidth improvement. As to the 75ns RAMBUS latency of on die controller, most of that is inherent to RAMBUS and probably assumes the fastest RIMMs with few memory dies. 54ns is the inherent amount for PC2700 CAS2 and that is whether 1 single sided DIMM or 2 double sided DIMMs are used. Pete