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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: dale_laroy who wrote (76249)	4/2/2002 8:34:23 PM
From: Dan3	Respond to of 275872

Re: This insistance of small die size is a disaster in the making. It erased all the strengths of Athlon processor performance-wise. Athlon can cache 6144 locations, while P4 is limited to 4096 locations. Now add to that the fact that Athlon's cache is 20-way, while Intel's cache is 8-way. There's more to a cache than raw size, there is line length, and discrete vs. unified (among other things). As far as running programs is concerned, AMD effectively has a bigger cache with an L2 of 256K than P4 does with an L2 of 512K. AMD could use a faster FSB at this point, but that doesn't require a larger die. Athlon was designed for 400mhz FSB, I'd like to see them start shipping at those speeds. Even nicer would be if they could tweak the Athlon bus a bit, and take it to 533. P4 wouldn't stand a chance... But I think the next place for AMD to tweak Athlon is FSB, not cache size, which means there's no point in increasing die size.

To: dale_laroy who wrote (76249)	4/2/2002 8:43:52 PM
From: niceguy767	Respond to of 275872

dale: Just not enough data in all merits of small die vs. merits of large die...Right now INTC has product with large die so many are hopping on the large die hypewagon...Let's see what happens over the next 9 months...TCMAYbe even JC's reviews, may be whisling a new tune 9 months out!!!

To: dale_laroy who wrote (76249)	4/2/2002 10:19:49 PM
From: Joe NYC	Read Replies (2) \| Respond to of 275872

Dale, I agree here, to a certain extent. I don't think that TBred will clock high enough for the limited amount of L2 cache to matter, but Barton should probably have 512KB L2 cache. The only way that I see for AMD's decision to cripple Barton with only 256KB L2 cache is if Clawhammer really does ship in volume in October. If you can't sell out your capacity for 6 quarters in the row, with transition to .13u adding even more capacity, any idea of crippling performance of a processor to make it less desirable is a bad one. Barton with 512K L2 would be a performance notebook chip, (bigger L2 would justify higher QS rating). Barton without small L2 will command (I mean lose) price differntial that is much bigger than cost of adding 256K L2 on .13u process. If AMD can make the transition to Clawhammer as rapidly as they made the transition from K6 to K6-2, repositioning Barton to occupy the same market segment as Intel's 130nm P-III Celeron did in Q4 of last year, while flooding the Asian markets with Morgans out of Fab25 and Appaloosa in a manner similar to what Intel did with low end Celerons in Q4 of last year, the decision to limit Barton to 256KB L2 cache could prove to be an excellent one. But these are big ifs. Well, I doubt there will be any flooding of any market with Austin chips. The .18u Al process is going to run out of steam. This is what AMD should have done in Q2, Q3: - Rename Palomino from AXP to Duron - Sell Tbred with 512K L2 in desktop and mobile - ramp down .18u Palomino Duron, transition capacity to SOI - ramp up Barton (with 512K L2) to replace Tbred in notebook segment (possibly some in notebook) - disable half of Tbred L2 (or salvage the ones with defects in half of L2) and sell it as Duron - augment 256 Tbred Duron with chips from foundry (if there is demand - forget Clawhammer, just do Sledgehammer with disabled HT links The end of 2002 lineup would be: - low end 256K L2 Tbred Duron from Dresden and foundry (desktop and notebook) - notebook Barton with 512K from Dresden - 1MB L2 Sledgehammer with 2 memory channel for desktop, 2 way server If AMD can get the yields to the same level as on the .18u copper process, the blended average die size would not be any bigger than that of Dresden output today (a big if). Today, it is 120 mm^2 (and some change) If we assume: - 256K L2 Tbred 80 - 512K L2 Barton 100 - 1MB L2 Sledgehammer 150 The ASPs would match Intel's $150, and to produce the same revenue as in Q4 2001, all AMD would need to sell is about 4.5 million units. These products would be in sufficient demand that AMD could sell all they could produce, which IMO could potentially up to twice 1.5 or 2x the 4.5 million, plus output from the foundry. The plan for 2003 would be to: - tranistion Duron from 256K L2 Tbred to 512K L2 Clawhammer - selling Sledgehammer DP and MP with cHT qualified - notebook chips would continue to be 512K Barton and 256K Tbred (for low end) Once again, I more or less agree. AMD needs to produce a "crippled" variant of the 90nm Sledgehammer for the desktop. Such a processor might have the same number of HTT links and DP capability like the DP Clawhammer, but be sold into the desktop market at the same peak selling price as Prescott. The 90nm Clawhammer would then need to be reduced to just 256KB L2 cache and marketed against P4 Celeron, perhaps being produced using bulk silicon for economy. But, even for this to work, AMD's transition to 90nm would have to take place within four month of Intel's. This is going into the future, but I think you have it backwards. AMD needs a crippled Sledgehammer (Clawhammer), but later on, potentially, after the demand for high ASP demand has been satisfied. What you do is produce the product that has the highest potential performance ASAP, get the highest ASP possible, and move it downmarket later on. On 90nm front, it will be at premium originally, so the highest ASP parts should move there first, which is 1 MB (or higher for servers) L2 Sledgehammer and notebook Hammer would move there first. It is not at all in AMD's interest to sell any $60 parts. AMD's desire should be to make (and sell) parts that command the highest premium possible. Today, it means 512K L2, 12 months from now it will be 1MB. I can't believe how AMD has missed the boat, and will end up being forced to sell the CPUs for sub-$60. Joe