Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (76278)	4/2/2002 11:58:06 PM
From: dale_laroy	Read Replies (1) \| Respond to of 275872

If you can't sell out your capacity for 6 quarters in the row, with transition to .13u adding even more capacity, any idea of crippling performance of a processor to make it less desirable is a bad one. Barton with 512K L2 would be a performance notebook chip, (bigger L2 would justify higher QS rating). Barton without small L2 will command (I mean lose) price differntial that is much bigger than cost of adding 256K L2 on .13u process. The only ways that the transition to 0.13-micron can add capacity is if Fab25 continues producing processors, or percentage yields increase dramatically, or Appaloosa accounts for a high percentage of Fab30's production. AMD probably used 80% of Fab30's capacity to produce 4 million processors in Q4 2001. The ramp to full capacity should have increased this to about 5 million processors at 0.18-microns. AMD claims 200 Palomino candidates per wafer versus 315 Thoroughbred candidates per wafer. Assuming the same percentage yield, Fab30 would be able to produce only about 7.75 million Barton processors at full conversion. Factor in that perhaps half of Fab30's production would be Appaloosa and this would increase to about 9 million processors. But, while all wafer starts will be 130nm by the end of the year, full production shipments will probably not be reached until Q2 2003. >Well, I doubt there will be any flooding of any market with Austin chips. The .18u Al process is going to run out of steam. This is what AMD should have done in Q2, Q3:< - Rename Palomino from AXP to Duron This would have been a bit premature, unless Fab25 would have been shifted to Palomino production. - Sell Tbred with 512K L2 in desktop and mobile This could have been a reasonable strategy, especially for mobile. - ramp down .18u Palomino Duron, transition capacity to SOI This could have been accompanied by the transition to Appaloosa Duron, emulating Intel's tansition from the 130nm PIII Celeron with 256KB L2 cache to the P4 Celeron with 128KB L2 cache. - ramp up Barton (with 512K L2) to replace Tbred in notebook segment (possibly some in notebook) The failure to do this will probably be AMD's biggest shortcoming. - disable half of Tbred L2 (or salvage the ones with defects in half of L2) and sell it as Duron With P4 Celeron having just 128KB L2 cache, Appaloosa should do just fine in this market. - augment 256 Tbred Duron with chips from foundry (if there is demand Foundry should be used for production of Appaloosa. - forget Clawhammer, just do Sledgehammer with disabled HT links Sledgehammer will be huge at 130nm, larger than Northwood, and with nine layers of metal interconnects. With dual DDR mobos for P4 not being common in Q4 of this year, or even Q1 of next year, Clawhammer is the better processor to go with. However, by Q2 2003 AMD would be feeling the pressure from a lack of a dual DDR Hammer on the desktop. And with the emergence of Prescott, 1 MB of L2 cache could also become desireable. The end of 2002 lineup would be: - low end 256K L2 Tbred Duron from Dresden and foundry (desktop and notebook) SHBE Appaloosa from Dresden by end of year. - notebook Barton with 512K from Dresden Agreed. - 1MB L2 Sledgehammer with 2 memory channel for desktop, 2 way server This would be premature. Desktop should have 512KB L2 cache with dual channel PC 2700 DDR SDRAM, and be DP capable. If AMD can get the yields to the same level as on the .18u copper process, the blended average die size would not be any bigger than that of Dresden output today (a big if). Today, it is 120 mm^2 (and some change) If we assume: - 256K L2 Tbred 80 - 512K L2 Barton 100 - 1MB L2 Sledgehammer 150 With this blended average die size for 130nm, Dresden might not be capable of more than 5 million processors per quarter. >The ASPs would match Intel's $150, and to produce the same revenue as in Q4 2001, all AMD would need to sell is about 4.5 million units. These products would be in sufficient demand that AMD could sell all they could produce, which IMO could potentially up to twice 1.5 or 2x the 4.5 million, plus output from the foundry.< Foundry shipments will not come online until Q1 2003, so you might be talking a 10% increase in revenues over Q4 2001. >The plan for 2003 would be to:< - tranistion Duron from 256K L2 Tbred to 512K L2 Clawhammer No! Appaloosa should remain low end Duron with 256KB Barton becoming high end Duron in H1. H2 should see 256KB Barton becoming low end Duron with 256KB Clawhammer becoming high end Barton. - selling Sledgehammer DP and MP with cHT qualified - notebook chips would continue to be 512K Barton and 256K Tbred (for low end) A Clawhammer with 512KB L2 cache should also be available for notebook. >This is going into the future, but I think you have it backwards. AMD needs a crippled Sledgehammer (Clawhammer), but later on, potentially, after the demand for high ASP demand has been satisfied. What you do is produce the product that has the highest potential performance ASAP, get the highest ASP possible, and move it downmarket later on. On 90nm front, it will be at premium originally, so the highest ASP parts should move there first, which is 1 MB (or higher for servers) L2 Sledgehammer and notebook Hammer would move there first.< Presumably this is why Intel introduced the 130nm Tualatin first, then 130nm P-III Celeron, then Northwood. To a certain extent I agree however. Mobile and MP should move to 90nm first, and it might make sense to replace the 130nm 512KB L2 cache Clawhammer with a 130nm 256KB L2 cache Clawhammer as the 90nm dual DDR desktop is introduced. > It is not at all in AMD's interest to sell any $60 parts. AMD's desire should be to make (and sell) parts that command the highest premium possible. Today, it means 512K L2, 12 months from now it will be 1MB. I can't believe how AMD has missed the boat, and will end up being forced to sell the CPUs for sub-$60.< I disagree here. Growing the market requires cheap parts, and AMD should always have at least one part under $50.

To: Joe NYC who wrote (76278)	4/3/2002 8:59:55 AM
From: hmaly	Respond to of 275872

Jozef Re...Barton without small L2 will command (I mean lose) price differntial that is much bigger than cost of adding 256K L2 on .13u process.<<<<<<<<<< True, but it will take engineering resources to redesign the cache, plus trial samples etc. which take time. Barton should do well until Banias, at which time Barton will have to be upgraded; however Clawhammer should be here by then, and Jerry can free up engineering at that time. Jerry has stated several times that Hammer takes priority. Why do a Elmer and think Jerry is lying. Jerry should have a better idea than you or I where AMD's limited resources should be spent.