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To: combjelly who wrote (163629)	4/6/2002 9:02:17 PM
From: wanna_bmw	Read Replies (1) \| Respond to of 186894

Combjelly, Re: "As far as the errata, yes it is the logic design and not the process. But it is easier to debug the individual cells if you aren't going over them and tweaking the transistors." I don't understand what you are saying. When you debug a post silicon problem, it has nothing to do with tweaking any sort of transistors. Whether the design used custom or standard cell libraries, it will be completely transparent on the system level. Yes, there are other kinds of validation on the transistor level, but those validators don't list their problems amongst "errata". I believe you might be confusing two different levels of validation, and somehow trying to argue the advantages of a cell based design at the same time. My suggestion is that you stop trying to argue on topics that you don't fully understand. wbmw

To: combjelly who wrote (163629)	4/6/2002 9:29:22 PM
From: Elmer	Read Replies (1) \| Respond to of 186894

As far as the errata, yes it is the logic design and not the process. But it is easier to debug the individual cells if you aren't going over them and tweaking the transistors. A bug is when the device says 2+2=5. Errata is when the device says 2+2=4 most of the time but under a very unique set of conditions it may say something else, maybe and most of the time nobody cares anyway. It's not because of the transistors in the standard cell are miss sized. It's because the designers screwed up and designed some logic incorrectly. Whether the design is implemented in a gatearray, standard or custom cells, the logic is wrong. If for some reason the transistors in the standard cell are not the optimal choice or the process has run out of gas and the device doesn't return the same answer under all conditions (temp & voltage), then you must screen for it and you have a yield or binsplit problem. EP