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To: ptanner who wrote (80790)	5/28/2002 12:34:24 AM
From: Ali Chen	Read Replies (2) \| Respond to of 275872

"New article over at Aces" I would not put much weight on this writings. The following excerpt from the article shows that the author does not quite know what he is talking about: “DMA introduces two problems however - if the I/O system uses DMA to write to the memory system, and changes some data that the CPU has cached, then unless the CPU re-fetches the cache line from memory, it will not get the new data. In practice, this is solved by some additional logic in the memory controller that informs the CPU of a DMA write, and the CPU invalidates (flushes) the relevant cache line. Alternatively, the I/O system could copy the data for updates to the CPU's bus, so that the CPU can pick up changes immediately. The second method has lower latency, but uses bandwidth inefficiently.” - Ali