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To: Ali Chen who wrote (80800)	5/28/2002 12:39:02 AM
From: ptanner	Read Replies (1) \| Respond to of 275872

Ali, re: "I would not put much weight on this writings." The writing was pretty rough and I just took it for entertainment. If with even my limited knowledge some of the statements appear questionable... well, thanks for second perspective. It was quite involved (appearing) for a general web article. -PT

To: Ali Chen who wrote (80800)	5/28/2002 2:42:03 AM
From: wanna_bmw	Read Replies (1) \| Respond to of 275872

Ali, Re: “DMA introduces two problems however - if the I/O system uses DMA to write to the memory system, and changes some data that the CPU has cached, then unless the CPU re-fetches the cache line from memory, it will not get the new data. In practice, this is solved by some additional logic in the memory controller that informs the CPU of a DMA write, and the CPU invalidates (flushes) the relevant cache line. Alternatively, the I/O system could copy the data for updates to the CPU's bus, so that the CPU can pick up changes immediately. The second method has lower latency, but uses bandwidth inefficiently.” Why must you have a beef with everything? I don't think the guys at Ace's are too far off here. In the first situation, they are saying that an inbound memory write needs to flush those cache lines from the CPU caches, which is correct, except that they forget to mention that modified data needs to be written back, first (a small technicality, and given their audience, I wouldn't penalize them too much for this). The second option might be specific to a kind of cache coherency that I am not familiar with, but how would you be certain that such an implementation doesn't exist? I'm sure you could create a controller with some kind of snoop cache that copies inbound write information into caches that are in one of the owned states. That would also maintain coherency, unless you can think of a corner case where it wouldn't. IMO, it would just be a waste of silicon, since a snoop cache would be required on the memory controller. wbmw