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To: wanna_bmw who wrote (80862)	5/28/2002 7:30:07 PM
From: Petz	Read Replies (2) \| Respond to of 275872

wanna_bmw - Please admit that you were simply WRONG when you implied that a cache-line "invalidation" ALWAYS results in that cacheline being FLUSHED and WRITTEN INTO MEMORY. It just AIN'T SO. You admitted this in your own post when you added qualifications to your statement that "invalidation" and "flushing" were the same thing. Your post: "Flushing" and "invalidating" are the same thing, as long as a line is owned by a caching device (processor or I/O hub), but is not in modified state. If the line has been modified, it will get written back to main memory. Yea, and if the line has NOT been modified, it is a waste of bandwidth to write it back to main memory. Petz

To: wanna_bmw who wrote (80862)	5/28/2002 7:53:15 PM
From: Petz	Read Replies (1) \| Respond to of 275872

<I am well aware of how some chipsets implement these ["invalidate transaction" and "flushing of data"] as different transactions> Any chipset that does not recognize these as different transactions cannot possibly work. "Flushing of data" is simply one of several possible responses a CPU might have to an "invalidate transaction." In fact, it is one of the LESS LIKELY responses in a 4-way system. BTW, calling people "obnoxious" and "jerk" is not allowed on this thread. Petz