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To: semiconeng who wrote (80972)	5/29/2002 2:54:33 PM
From: THE WATSONYOUTH	Read Replies (2) \| Respond to of 275872

And as far as the Notched Poly, who says intel "have to use" Notched Poly to achieve 0.18u Gate lengths. 0.18u started out without Notched Poly and achieved the required Gate lengths. Notched Poly was a Process Improvement put in by The Process Engineers, not the Development Engineers. If I find something that Speeds up my chips, I use it. besides, who says it's been abandoned? How Notched Poly came to be is actually a really interesting story, but somehow, I don't think (based on your "half assed" comment) that you're really interested in an answer at all. So... you claim they started .18um (at longer channel lengths) with out it and as .18um started to approach its minimum channel length, they implemented the notch process. Sounds like they thought they needed it to me. But they use the same lith tools at .13um at MUCH smaller channel lengths and they now don't need it. Somehow, I doubt phase shifting could have allowed that much smaller gates. Maybe the notch process was the cause for that 1.13um GHz fiasco and 1.1 Ghz parts were only introduced many months later after the notch process was canned and the process they use at .13um substituted. And what "process engineer" discovered this now famous/infamous notch process? Might it have been one "Charles Chu" whose name mysteriously appeared on the IEDM paper that describes the notch process but was not heard from before or since??? Give Chucky a hello for me. -- And that's the fly in your ointment, "Carefully Controlled". Achieving what you sugest may have been fine for your buddies at IBM and low volume, but to maintain those line widths using the techniques you suggest, was determined to be far too labor intensive, too costly, and too slow throughput for high volume manufacturing. Gate line width control is everything. You do what ever you need to optimize it The payback for being able to consistently work near minimum channel length with excellent within chip/chip to chip/ wafer to wafer/ and lot to lot control is enormous. There is nothing about the RIE trimming technique which is too slow or costly for high volume manufacturing. You are simply wrong there. THE WATSONYOUTH