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To: Petz who wrote (84763)	7/12/2002 5:31:02 PM
From: wanna_bmw	Respond to of 275872

Petz, Re: "(130M sellable CPUs)/(80K wspw x 2/3 utilization rate x 0.6 fraction used for CPUs x 52 weeks) = 78 sellable CPUs per wafer, running at 2/3 capacity. Close to the number you get if you do the calculation for AMD. Still, less than 50% yield and not "world class" according to Elmer." First, Elmer has never attributed the ratio of sellable CPUs to total die on a wafer as ever relating to yields. He has stressed many times that his definition of good yields is dependent on defect density, which is totally different than the number you calculate. Second, Intel has reached the point where the majority of their CPUs must be made at .13u. They still have .18u Celeron parts and .18u McKinleys, so it's not near 100%, but they have definitely surpassed 50% by now. I calculate 75k wspw from the TSMC number (332k(.051/.052)(12/52)), but only a fraction of this is .13u right now. So how in the world can you assume that 32k wspw (802/3.6) is going towards CPUs? No way has Intel moved 43% of their entire capacity to .13u in one year. It took them nearly a decade to accumulate the kind of manufacturing that TSMC quotes. If I were to make a SWAG, I would list the wspw from Intel's .13u fabs (keeping in mind that Intel still has a long way to go before they are ramped up in their .13u fabs), add 20-25% for remaining .18u CPU production, and use that to calculate the ratio of sellable die to total die per wafer. But that still won't give you defect density with which to compare to Elmer's claim; nor will it give you bin splits, or any other useful measurement for comparison. wbmw

To: Petz who wrote (84763)	7/13/2002 12:40:11 AM
From: burn2learn	Read Replies (2) \| Respond to of 275872

Based on the TSMC numbers, current capacity is a little higher, more like 80K wspw, but thats a minor quibble. And I said that only 60% of "conceivable fab space" was being used for production CPUs. Now, Intel might not be running this space at 100% capacity. If they are running at 2/3 capacity and they sell 130M CPUs in 2002 (4x the rate of Q1, which is usually above Q2, equal to Q3 but below Q4), the Good Die Per Wafer (GDPW) is (130M sellable CPUs)/(80K wspw x 2/3 utilization rate x 0.6 fraction used for CPUs x 52 weeks) = 78 sellable CPUs per wafer, running at 2/3 capacity. John, This answer is very simple for me, I get to see a spreadsheet of current loading by product and projected plans for next few years by quarter for every process and product. For you....you have a long way to go to be able to get to ballpark numbers. I will point out a few things and hopefully the forum can strive to get ballpark numbers for each piece of the pie. 1. you need an accurate list of fabs and forget the space and focus on wsw and current capacity loadings compared to full loadings. 2. develop a pareto for what products run on what processes and determine die size for each. 3. get a number for engineering lots for each process. you can't improve a process without engineering lots that have experiments ran on them, also a list future products and loadings of these to get them production worthy. 4. maybe a graph of gap to capacity capability vs outs to determine yield for each product / process. then show each separately. I can tell you for some products on some processes 78 die per wafer is kicking butt!! 5. It’s amazing but some products that Intel currently makes are on a process >1 micron and is sold out! These are legacy products made in Israel on a 6” wafer and are sold out for many years to come. How many die on a 6” wafer, and what are they? Fab 1-7 do they exist, how about Fab 8 what does it make? List your Fabs and how you think they are loaded for products. given ASP's and the fact that you know GM's do you need to do this exercise to know something must be running good. Why can you not assume yields are great and there is more to this than you can understand with the disclosed information?