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Technology Stocks : Semi Equipment Analysis -- Ignore unavailable to you. Want to Upgrade?

To: StanX Long who wrote (10944)	8/11/2003 10:43:36 PM
From: Gottfried	Read Replies (3) \| Respond to of 95738

Stan, that list is a bit beyond my capabilities but I hope some others will find it useful. Gottfried

To: StanX Long who wrote (10944)	8/12/2003 11:34:09 AM
From: Kirk ©	Respond to of 95738

FSG ILD I thought I knew what FSG was but I didn't know what ILD was... So trusty Google yields a great paper on it from Intel: intel.com The process is to lower the interconnect delay.... INTERCONNECTS Chip performance is increasingly limited by the RC delay of the interconnect as the transistor delay progressively decreases while the narrower lines and space actually increase the delay associated with interconnects. Using copper interconnects helps reduce this effect. This process technology uses dual damascene copper to reduce the resistances of the interconnects. Fluorinated SiO2 (FSG) is used as an inter-level dielectric (ILD) to reduce the dielectric constant; the dielectric constant k is measured to be 3.6. Figure 17 is a cross-section Scanning Electron Micrograph (SEM) image showing the dual damascene interconnects. That photo they show is a cross section of a chip clearly showing 6 Copper metal layers. I believe the bottom (first) layer is Polysilicon which is needed to make clean, good contacts to the transistors. Here is the full article in PDF intel.com a real keeper! Kirk