To: Road Walker who wrote (176450 ) 1/10/2004 2:34:31 PM From: Gary Kao Read Replies (1) | Respond to of 186894 New Business for Intel: 60% share of PDA CPUs!! from the Microprocessor Watch *** Intel 2003 Analyst Meeting Notes Kevin Krewell - Senior Editor (12/08/2003) At the annual Intel analyst meeting, held this year on November 20, 2003, the company talked optimistically of a return to normal industry growth. But not all Intel's businesses are growing at the same rate, and not all geographies are growing at the same rate. The present geographic split of Intel's business revenues has only 30% coming from the Americas, still the company's largest market. The company believes the opportunities for real double-digit growth, though, are in China, India, Russia, Eastern Europe, the Middle East, and Turkey. The company's strategy is to provide standard building blocks, built around Intel silicon, to growing markets such as telecom and enterprise servers. Intel's goal is to move target markets away from "proprietary" solutions and into standardized solutions having increased amounts of Intel silicon content--taking the PC business model into these markets. The real advantage of Intel's strategy is not necessarily product superiority but the transfer of some R&D expenses from the systems vendors to Intel. With its XScale and StrongARM processors, Intel claimed a 45% market share in PDA processor shipments and projects its share will grow to 60% by the end of 2004. Intel believes itself well positioned for big growth in cell phones in 2004 and hopes to get 10 million units in that year. Intel also made a point that it wants to be number one in NPU processors. Even as Intel has been struggling to ship its 90nm products, the company announced a key milestone on the road to 65nm--the first fully functional SRAM chip produced in 65nm. The new process (P1264 in Intel's nomenclature) has a 35nm gate length and uses the same low-k CDO dielectric and strained silicon that 90nm uses. It will support up to eight layers of copper interconnect. The key design element is a 0.57-square-micron six-transistor memory cell. Microprocessor Report subscribers can access the full story here (2 pages): mdronline.com