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To: TigerPaw who wrote (177971)	5/14/2004 3:16:28 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 186894

TP, Correct, the OS involvement comes in when tasks are swapped. OK, but tasks are swapped how often compared to the billions of cycles run on modern-day processors per second? A swap is going to adversely affect any multiprocessor system as the caches realign their data to the new tasks. Fortunately, such swaps don't occur very often. Even when the OS has not swapped the task to a different chip the protocol has to check because it has no other indication. Sigh, I don't know how many times this needs to be repeated. The cache protocol has NOTHING to do with the OS. I REPEAT: The cache protocol has NOTHING to do with the OS. Any cacheline in Modified state is not going to be checked on the bus until the other processor requests it. In your context of a task switch, that request won't come until the task switch actually occurs. Until then, the processor that owns the Modified cacheline does NOT have to issue coherency checks on the bus every time it accesses the data. Once again, we're going in circles here. I believe it is because you are not familiar with bus protocols or cache coherency protocols. I don't like to repeat myself, so if I can't convince you, I'll drop the subject and let you have the last word. Tenchusatsu