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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Pravin Kamdar who wrote (133615)	9/23/2004 5:43:34 PM
From: dougSF30	Read Replies (1) \| Respond to of 275872

Pravin, It does matter how the deck chairs are arranged. Keeping a high-volume part on 130nm when they are trying to convert from 130nm to 90nm doesn't make sense. And I'd be nervous with selling 3100+ 130nm Semprons at near break-even or a loss, while saying, well, we'll make it up because we'll have better margins on those extra Winchesters that replace the Newcastles we Semproned... it is mathematically equivalent if nothing goes wrong... but I would rather be selling clearly profitable 90nm Sempron 3100s, and making a little less profit on some Newcastles that fill in for the Winchesters (ni that case). Regarding mobile, I'm not sure you can infer that much about overall 90nm binsplit progress from Low Power mobile plans. AMD still has a bit to go to match Dothan power levels. If going with a 1Mb L2 114mm^2 die helps them get there, they should do that. Doug

To: Pravin Kamdar who wrote (133615)	9/23/2004 6:11:01 PM
From: eCo	Respond to of 275872

Pravin:If we assume that they are at (or near) full capacity, then it does not matter how the deck chair are arranged. What would be important is to have chips on the newer process that could be sold with any value add that that process might give them. I agree with the second part above, but not necessarily the first. The first would be an interesting ops research problem which would take into account the dynamics of the time it takes to bring 90nm on line, the increased margins 90nm would bring, and the volumes of the various market segments each product addresses. But to your main point about binning, it is a fact that AMD owns the high speed segment at the moment on 130nm, and this will apparently continue for some months. So speed would fail your criterion for adding value at this point in time, and I would therefore not expect it to be a priority. That said, it doesn't preclude a binning problem which your example, if real, does seem to support. eCo

To: Pravin Kamdar who wrote (133615)	9/23/2004 6:15:16 PM
From: pgerassi	Read Replies (3) \| Respond to of 275872

Dear Pravin: There is no wall at 2GHz since any A64 90nm 3500+ 939 is already at 2.2GHz. 2GHz 754s at 35W AMD TDPmax may roughly use the same power as 21.5W Intel TDPtyp 2GHz Dothans. By using AMD's definitions and calculation methods, 1.6, 1.8 and 2GHz Dothans use 30.6W TDPmax and given AMD's use of family ratings, easily could be called 35W TDPmax CPUs. Where are the 2.2GHz@800FSB Dothans? Given that a 35W MA64 2800+ runs at 1.8GHz and that 2.4GHz A64s use the same process, it is reasonable to assume that a 35W 90nm MA64 3000+ could run at 2.6GHz using less than 89W. Furthermore, it is reasonable that a 90nm Opteron x46EE (2GHz@35W) can be made which then given x40EE and x46HE on the same process yields a x46EE and a x54HE (2.8GHz@55W) with a x58 (3.2GHz) or x60 (3.4GHz) being the top bin. Of course, 65nm could come soon enough to make the top 90nm bin lower. We will know what the top bins are likely to be once overclocking sites use the 90nm A64 versions. Pete

To: Pravin Kamdar who wrote (133615)	9/23/2004 6:56:23 PM
From: Elmer Phud	Respond to of 275872

Pravin If we assume that they are at (or near) full capacity, then it does not matter how the deck chair are arranged. If you assume that then you have the problem of explaining why the output is so low. Full capacity producing ~1/2 to 2/3rds the expected output leads to an unpleasant conclusion. In this case low demand is the better problem because that can be fixed without solving difficult technical problems. Moving to an even more difficult process and expecting high output when a mature process results in low volume is not realistic. But this is the AMD thread and wishing can make it so.

To: Pravin Kamdar who wrote (133615)	9/23/2004 10:18:41 PM
From: Joe NYC	Read Replies (1) \| Respond to of 275872

Pravin, On another note, I agree with Petz that it is looking like AMD has hit a frequency wall on 90nm (at least for now). There was an article on xbitlabs stating that new mobile chips in Q1 will still be 2.0Ghz, but will double the cache to 1 Meg to squeeze out a higher model rating (the link isn't working for me right now). This increases the cost of production, and they would not do it if they could just bump the speed. Actually, I disagree. It makes sense to have a bigger cache on mobile chips to achieve a given performance level for number of reasons: - This performance level can be achieved at lower power (because of lower clock speed and possibly lower voltage) - mobile solutions are single channel, bigger chache has a bigger bang in that scenario vs. dual channel - fewer cache misses mean fewer memory accesses, which probably mean lower overall power consumption Now, on the desktop, the situation is different, and the rumors that 3500 (2.2 GHz) is the highest clock speed available is more worrying. Rumors of chips such as 2.2 GHz and 1 MB L2 (3600?) may be indications of what you are talking about. From a customer point of given a choice of equal approximate performance, I would always chose lower clocked one with bigger L2. From AMD point of view, it is just the opposite (if higher clock speeds are achievable). Joe