To: pgerassi who wrote (133622 ) 9/23/2004 6:23:56 PM From: dougSF30 Respond to of 275872 Pete, I think we'll have to wait a bit longer to figure out the top bins for 90nm. Why? Because these initial 90nm parts are the "straight shrink" of 130nm. Remember that AMD said they were then going to add two metal layers, and relayout the core. I'm guessing that is what the E0-rev is, in addition to SSE3 and other improvements. Let me find the reference:investorshub.com By Peter Clarke Silicon Strategies 04/19/2004, 12:09 PM ETsiliconstrategies.com MUNICH, Germany -- U.S. processor and flash memory maker Advanced Micro Devices Inc. has begun using a 90-nanometer silicon-on-insulator (SOI) manufacturing process at its Fab30 in Dresden, Germany, according to Thomas Sunderman, a director of manufacturing technology within AMD's corporate manufacturing group. AMD expects commercial shipment of products made using the 90-nm process to begin in the third quarter, Sonderman said. The move saves about 40 percent of the die area compared with the established 130-nm process and should have a similar bearing on AMD's costs until the company introduces 300-mm wafer processing now expected early in 2006. The 90-nm AMD64 is in active pilot mode in Fab 30 and prototype parts are running in systems, Sonderman said. Sonderman added that strained-silicon would be introduced by AMD at the same manufacturing process node. Although no official word was given on the first product to migrate to the 90-nm process, all the material in a presentation from Sonderman given the day before the Semicon Europa exhibition here, referred to the AMD64 family of Opteron and Athlon chips and the AMD 64-bit Opteron processor in particular. "There are no plans to migrate the classic Athlon to 90-nm," Sonderman confirmed. Sonderman said that the 90-nanometer process would come in with all the advanced features acquired during previous generations; including copper interconnect, a Black Diamond low-k technology, and as an SOI process with the base wafers provided by Soitec SA. The combination would give a "significant power saving," Sonderman said, but refused to quantify this saying it would be revealed when AMD announces 90-nm products. In its 130-nm SOI process an Opteron with an 8-Mbit cache occupies 194 square millimeters but the move to 90-nm has reduced the die size to 114 square millimeters Sonderman said showing the prototype die in his presentation.The 90-nm process has started with a nine-layer interconnect back-end to match the 130-nm process to allow easy transition of established products, but that for new or re-laid products the process would be extended to 11 layers. Sonderman said the use of SOI at the 130-nm process node had reduced processor power consumption to the 45-W to 55-W mark and that the shrink to 90-nm would produce an additional benefit. "It's reducing power significantly...gives AMD the freedom to boost performance or lower power." When asked what features would be added to the process Sonderman said: "Strained silicon is one of the things you are going to be seeing from AMD at 90-nm."