Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: etchmeister who wrote (148715)	1/22/2005 12:22:52 AM
From: Elmer Phud	Respond to of 275872

etchmeister 156 x 2 = 312 (assuming size = 2x) 312 GDPW versus 428 GDPW; is the difference strictly due because larger die causes more silicon real estate loss at the edge? The 156 GDPW estimate was based on the assumption that Smithfield is a single die and is 2X the size of P4. Also assumed is that Intel has excellent yields. I make no claims that either of these are actually the case. You be the judge. So there's no reason to multiply it by 2 again.

To: etchmeister who wrote (148715)	1/22/2005 12:30:05 AM
From: burn2learn	Read Replies (1) \| Respond to of 275872

Since I'm looking from Capex point of view my two cents input is that they will need more equipment to realize similar output (SC versus DC); also additional layer of copper Why an additional copper layer, where did you get that. I was trying to explain in my post earlier that the bebifit of lower DC speed parts (not agressive at poly) gives yield loss of ~1-2%, compared to SC parts on a BTQ process with ~50% loss and much less predictability since yield vs poly length is a cliff at this point. So not much impact to capacity.