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Technology Stocks : Applied Materials No-Politics Thread (AMAT) -- Ignore unavailable to you. Want to Upgrade?

To: matt dillabough who wrote (16779)	12/7/2005 8:31:32 AM
From: Proud_Infidel	Read Replies (1) \| Respond to of 25522

65 nm will change industry, analyst says Richard Goering EE Times (12/06/2005 11:30 PM EST) SAN JOSE, Calif. — From a technical standpoint, 65-nanometer design is easy — but it will change the entire semiconductor industry business picture and provoke a "competitive re-aggregation," said Gary Smith, chief EDA analyst at Gartner Dataquest. Speaking at the Gartner Dataquest semiconductor industry briefing here Tuesday (Dec. 6), Smith said that semiconductor vendors must design complete systems including embedded software, and move up to electronic system level (ESL) design. Design for manufacturing (DFM) concerns may bring about the end of the customer-owned tooling (COT) model and turn foundries into ASIC vendors, he said. "Contrary to popular opinion, 65 nm is turning out to be much easier to design than we thought," said Smith. "What it will do is change the semiconductor business picture dramatically." Semiconductor vendors, said Smith, will be forced to either upgrade their design capacity to meet competitive pressures, or downgrade their design capacity to meet cost pressures. Because companies did too much disaggregation in the 1990's, a wave of re-aggregation is coming, he said. With system-on-chip (SoC) design, Smith said, embedded software has become a major competitive design component. For EDA providers, it's an area of needed focus. "Software is by far the number one issue we have in design," he said. At 65 nm, Smith said, there is a major post-GDSII DFM design effort. With the need for resolution enhancement techniques, semiconductor design firms should consider bringing mask-making back in house, he said. Further, for DFM layout, compact process models are an "absolute must," but foundries won't give them to more than a handful of trusted, major customers. Without a secure, compact process model, IC layout will be brought in-house, spelling the end of the COT model, Smith said. He noted that foundries are starting to provide an "ASIC like" business model to their customers, and said that some "upper mainstream" companies have stopped doing IC layout and are passing designs off using a gate-level netlist. What these companies really need to consider, he said, is RTL handoff. Power users must continue to hold their design and silicon edge, Smith said, but they also must realize that the key to the new semiconductor market is applications knowledge. Thus, they cannot complete embedded SoCs without significant software content. "The 'S' in SoC stands for system, but the semiconductor guys don't understand that," Smith said. "You are designing systems. That means that ESL will bring an entirely new approach to the market."