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To: Magrathea who wrote (210424)	9/8/2006 12:39:55 PM
From: jspeed	Read Replies (1) \| Respond to of 275872

The cell architecture is essentially a Power core hooked up to 8 SIMD engines. It can theoretically produce huge IPC, but there are very few applications that can make use of this horsepower. I'm guessing that the interconnect is designed to feed these parallel engines in a way that would cause bottlenecks or impractical topologies with HTX. So a combined Opteron-Cell blade would probably use Opteron for conventional tasks and Cell for heavy lifting computational tasks. It makes sense to loosely couple the architectures as opposed to add an HTX interface to Cell.

To: Magrathea who wrote (210424)	9/8/2006 1:42:46 PM
From: Rink	Respond to of 275872

Mag, re: My read is that CELL will be the "dominant" chip in HPC if IBM pulls of the compiler auto-vectorization for CELL. Opteron becomes a manager of the CELL hive or executer of the portion of processes that need out of order execution. IBM will use only as many Opterons needed to make the CELL blades shine. A symbiosis, perhaps, but not a marrage of equals. Somewhat similar and even tighter integration will happen with Cray's Opteron systems with Vector processors. Opteron will be used for general purpose and in Cray's case also scalar computing, with both Cray's vector CPU's and IBM's Cell CPU's will be used for vertorizable code (mainly floating point for Cray, and both FP and INT for as far as I can see for IBM). (Besides this Cray will btw also have Opteron model's with Xilinx FPGA's.) My 2c: This (general purpose Opteron with special purpose 'co'-processing unit) is forming the basis of a major HPC model (it's not entirely new exactly but it's becoming way more popular now). Intel has been left out of this model largely because their interface that competes with HTT (CSI) is delayed. And it looks to me that there's a possibility that the reach of this model will be extended with 4x4, possibly even into workstations. Regards, Rink