Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: ChrisBBo who wrote (210922)	9/14/2006 4:12:50 PM
From: inex	Read Replies (1) \| Respond to of 275872

Chris, Based on your views, have you made any decisions on how to benefit financially playing either Intel or AMD, or, are you currently on the sidelines awaiting a more concrete opportunity??? Scott

To: ChrisBBo who wrote (210922)	9/15/2006 5:29:37 AM
From: brushwud	Read Replies (1) \| Respond to of 275872

Halving the area of a wire, halves its capacitance. If the wire is reduced equally (square root of 2 ~= 1.414) in both length and width, resistance stays the same. The combined effect is a wire that's "twice as fast". You're seeing the wire as a 2-dimensional entity, so R = L/W and C = LW. If L and W are each scaled by s, then R[s] = sL/sW = L/W = R and C[s] = sLsW = (s^2)LW = (s^2)C, so resistance is unchanged and capacitance scales by s^2, "halved" as you said. The "area" you're talking about is the area of a plan view of the wire and you're disregarding the lateral capacitance of the area of its profile. In other words, you're assuming that the height of the wire is negligible. If you think of the wire 3-dimensionally, with some significant height, then R = L/(WH) and C = LW + LH. Now if all three dimensions are scaled equally, R[s] = sL/((s^2)WH) = R/s and C[s] = (s^2)LW + (s^2)LH = (s^2)C. Just remember: area = capacitance = bad Length / width = resistance = bad OK, badbad = really bad, which is RC. To continue with the 3-d case, the scaled R[s]C[s] = (R/s)(s^2)C = sRC, so rather than being halved, the combined resistance and capacitance is only reduced to 70% of what it was before. Next, let's assume H doesn't scale. We're back to R[s] = sL/(sWH) = L/(WH) = R, so R doesn't scale, same as the 2-d case. But C[s] = (s^2)LW + sLH which is a hybrid of the simple 2-d and 3-d cases. If H << W, you approach the 2-d case and if H >> W, you approach the 3-d case. The other part of the circuit equation is transistor performance. The amount of resistance and capacitance in the transistor. This is very* simplified. Let's go one step further and introduce the gate capacitance of the transistor at the end of the wire. Again, R doesn't scale, but now C' = (s^2)LW + sLH + C[g]. This time you have a component of capacitance which doesn't scale, since the last 90 nm transistor = the first 65 nm transistor. You can't say RC is halved, you can't say it scales by 65/90, you can't say it scales by much at all, depending on the actual values of C[g] and H! Don't expect AMD's initial 65 nm parts to use so much less power that they go into the notebook market or to be so much faster that they go into the server market. Look for them to be so much denser and cheaper to make that they go into desktops.