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To: DDB_WO who wrote (210945)	9/15/2006 6:42:15 AM
From: Rink	Respond to of 275872

My K8L die size estimation is ~289 mm² By Dresdenboy (Recent posts) Monday, September 4, 2006 6:39 AM EDT aceshardware.com -------------------------------------------------------------------------------- So, I finally put everything together into one image with all stuff I have to say there :) Before that I calculated ~300 mm² die size for K8L based on the 65nm to 90nm comparison. Now I'm a bit below that with ~289 mm² but it should give a really good estimation. [289 mm² is for QC rev H including L3 cache] According to the 65nm to 90nm die comparison the prototype really shows 65 nm structures. I measured the width of some execution units, register files etc. and they show a scaling one would expect in this case. And before posting here I had an interesting and really long discussion regarding this stuff on W:O. Thanks to BavarianRealist for contributing there and giving me some points to be proven wrong or right ;) (as available facts permit) Sources: epscontest.com (K8L die plot) amd-images.de (300 mm wafer with 65 nm protypes) img132.imageshack.us (a first really good die size comparision of 65 nm prototype and 90 nm K8 rev. E) pc.watch.impress.co.jp (rev. F die photos and a table with infos on die/cache areas, btw, the border drawn on the rev. F die foto includes some stuff, which is actually not part of the die) -------------------------------------------------------------------------------- Link: wwwra.informatik.uni-rostock.de ========================================== Reply to DDB by Hans de Vries: ========================================== Serious core scaling problem, or ..... By Hans de Vries (Recent posts) Monday, September 4, 2006 3:15 PM EDT -------------------------------------------------------------------------------- Serious core scaling problem, or: preliminary low density layouts for functional testing only? The early "blue" 65nm prototype, single core, DDR1 I/O, which has an entirely rerouted core was the first possibility to measure the die size (based on the bump I/O distance). Your 102 mm2 seems in the right ballpark for the blue prototype. Now taking your die sizes for the SQ and QC 65 nm parts we get for the die and core sizes (excluding 2nd FP): __________________ die size / core size ___________________________ SC 130 nm HiP7: ____ 194 mm2 / 53 mm2 effective core scaling: 130 nm SC 100 nm Hip8: ____ 114 mm2 / 31 mm2 effective core scaling: 100 nm SC 65 nm AMD/IBM: __ 102 mm2 / 26 mm2 effective core scaling: _91 nm QC 65 nm AMD/IBM: __ 289 mm2 / 24 mm2 effective core scaling: _87 nm You see that the 65nm core is actualy as big as you would expect from a 90 nm process, that is, almost twice as big as it should be. Note that the optical shrink from 130 nm Hip7 to 100 nm Hip8 shows a perfect scaling: (130/100)^2 = ~1.70. (Hip8 was later renamed to 90 nm and there was one small die shrink to 106 mm2 afterwards) Now, if we at the other hand look at a megacell like the FP register file array then we DO see (almost) the scaling as expected: FP registerfile scaling: 130 nm Hip7: 1.41 mm2, effective scaling: 130 nm 100 nm Hip8: 0.85 mm2, effective scaling: 100 nm 65 nm proto: 0.41 mm2, effective scaling: 70 nm The point thus seems to be mainly the density of the routing. The question is if this is a problem which will remain, or that the dies we look at are only earlier prototypes for functional testing. For the latter you want working hardware as soon as possible and economy is not an issue. There has not been any picture out in the wild of Rev.G which is supposed to be an almost optically scaled version of Rev.F. One might expect that such an optical shrink simply wasn't possible in the beginning of the year. Remember, Intel could only go to 65 nm by NOT scaling metal layer 1 (only by 5%) This requires a complete new layout and new routing software which limits the routing at M1,M2 to only horizontal, vertical bars, (also in preparation to double illumination schemes). Now, with more advanced lithography systems, it might actually be possible for AMD to do a real (almost) optical shrink, much like it did when it went from HiP7 to HiP8. The core size of the prototypes has probably no relation at all to the core size of the 65nm Rev.G we will be seeing at the end of the year. It remains to be seen what the Rev.H core size will be by mid 2007 when there should be real volume production. Regards, Hans ========================================== Some select quotes from other posts in the thread: ========================================== DDB: Do you remember the Kevin McGrath and Jerry Moench talks at Stanford University? One of them mentioned additional metal layers and the resulting opportunity to use automatic routing. Another idea: Could increased space between units have any positive effect regarding hot spots? Hans: It turns out that the cores shown are only minimally smaller. This maybe better in the final product, I don't know. however, The impression that the L2 cache had become much denser was rather the result of the cores becoming relatively bigger. ==> No denser L2. Hans: The 65nm process is the first entirely together with IBM. Of Course, transistor improvements and other improvements were constantly added. freescale.com my-esm.com ============================================= DDB + Hans, very nice work. TX!!! Regards, Rink