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To: Joe NYC who wrote (212170)	10/1/2006 9:43:44 PM
From: combjelly	Respond to of 275872

"I am a little worried about integer, because that's an area that Conroe improved significantly" Well, doubling the bandwidth to the cache should help. As some of the other tweaks.

To: Joe NYC who wrote (212170)	10/2/2006 3:25:36 AM
From: Rink	Read Replies (1) \| Respond to of 275872

re: I am a little worried about integer, because that's an area that Conroe improved significantly (and K8 trails the most). I believe all SSE instructions are done by the FP units (including the INT SSE ones). I'm presuming this is correct, so my conclusion so far was that any DC rev H wouldn't trail CMW significantly in any area. It should lead somewhat in FP, and be quite close to on par with INT. The lead in FP is because in certain circumstances a DC rev H has a higher IPC, and the lead is a bit less than what it could be because CMW has larger total amount of cache. Comparing Kentsfield-alike QC's from Intel with the QC rev H the advantages of a better infrastruction should be highlighted even more in multiple socket systems (this plus FP performance is why I think Opteron continues it's string of design wins). The only thing that is unclear to me so far is if the third FP unit (FP MISC) has also been doubled (the analyst day slides are not clear but imply this is not the case; they do clearly show that both the FP ADD unit and the FP MUL unit have been doubled). Regards, Rink