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To: neolib who wrote (218948)12/5/2006 12:10:21 PM
From: j3pflynnRead Replies (1) | Respond to of 275872
 
neolib - I think that may be upcoming. Seems Hans' post on an upcoming presentation may have mentioned that. Maybe Barcelona will have it?

Message 23068721
Assuming that in "65nm 11M SOI CMOS process" 11M means metal layers. Anyone?



To: neolib who wrote (218948)12/5/2006 1:44:33 PM
From: RinkRead Replies (1) | Respond to of 275872
 
Partial comparison between AMD and Intel 65nm process:

AMD's 65nm process uses 9 copper layers + 1 Alu layer for metal layers, 35nm gate length, gate oxide thickness of 1.05nm (~4 atomic layers), and SRAM cell size of 0.65µm. ZRAM cell size should be 5x as small but might not get used at 65nm designs (Barcelona and some direct derivatives have taped out and don't use it, so it will not happen until start 2008 which is close to mid 2008 45nm process).

It compares to Intel's 65nm as follows: Intel uses 8 copper layers, 35 nm gate length, gate oxide thickness of 1.2nm (almost 15% thicker) which is the same as they used for their 90nm process (Hans mentioned this too), sram cell size of 0.57 µm.

The above's all from recent articles I read.

Regards,

Rink

PS, Neolib, there's a difference in the amount of metal layers the process is capable of and the amount that's actually used.