To: Tenchusatsu who wrote (225609 ) 2/8/2007 9:50:08 PM From: fastpathguru Read Replies (1) | Respond to Nope, actually you're the one who got a lot of things backwards. Xeon does it by relying on the north bridge to provide the bandwidth. Neither approach is really superior as long as the bandwidth is available. [emphasis mine] (Power, on the other hand, is a different story.) in theory. Is there a 4xFSB, 8xDDR2 channel chipset for Intel, and if so, what's the cost? Please don't make me go through the argument about how AMD's solution scales better, esp. at the 4S level... It's not theory but actual product that's been out for 4 years now.Secondly, AMD needs to make its L3 a victim cache because the size of it is "merely" 2MB. That's the same as the sum of the L2 caches, so it's obvious that a traditional L3 cache would have been useless. In other words, the necessity of the victim cache approach is driven by AMD's inability to match Intel's manufacturing strength. And third, it's not Intel who needs to catch AMD at the moment. It's AMD who needs to catch up to Intel. Don't count your chickens before they are hatched.
