Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: fastpathguru who wrote (225617)	2/9/2007 12:15:45 PM
From: Tenchusatsu	Read Replies (2) \| Respond to of 275872

FPG, good post. Just want to address one point: > Sure, in theory. Is there a 4xFSB, 8xDDR2 channel chipset for Intel, and if so, what's the cost? Please don't make me go through the argument about how AMD's solution scales better, esp. at the 4S level... It's not theory but actual product that's been out for 4 years now. Let me first clarify something. You said the following: > The margin of superiority is small enough that "bigger caches, hardware prefetches, and processor-specific compiler optimizations" are enough to overcome it... In a 1S system. That's not true. Bigger caches and everything that takes advantage of it makes a lot of sense in 4S systems as well. Think about it; the processors can spend less time accessing the memory if more of their working sets fit in their caches. Now to answer your question. There is a quad-FSB chipset coming out from Intel which will support Tigerton, Intel's direct response to Barcelona. Sure, it's not cheap (in terms of cost and power), but just like the multi-chip module concept, it's a pretty good stop-gap measure until Intel finally gets rid of the FSB. Tenchusatsu