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To: Saturn V who wrote (228588)	3/20/2007 7:29:35 PM
From: Rink	Respond to of 275872

(deleted; not relevant enough)

To: Saturn V who wrote (228588)	3/20/2007 7:42:06 PM
From: TimF	Respond to of 275872

But are Athlon, Opteron, Core2, Pentium 4, etc. 150um or thinner? Future chips, or other types of chips are irrelevant to this point. Well maybe near future CPU/MPU chips aren't irrelevant, but what chips does Intel have coming out that are so thin? And even if such chips do exist that's only another factor of 2 off your earlier estimate. However this link is talking about results on 25nm wafers. 25 µm not 25 nm. Big difference. And I really doubt this is relevant to current or near future CPUs or GPUs Also see Rink's post. Edit - He deleted it. I'm not sure I understand why. Edit again - So see this instead Message 23386038

To: Saturn V who wrote (228588)	3/20/2007 8:17:28 PM
From: pgerassi	Read Replies (1) \| Respond to of 275872

Dear Saturn_V: From the mouths of Intel, here is an article of the 0.13um P4 generation: When the process is complete, the resulting dies may be thicker than the 1mm where they started. ( Die is what the individual processors are called once they've been separated from the wafer.) smartcomputing.com So even Intel at the time Bohr made those claims were using wafers that were 1mm thick (1000um or 1000000nm). And 130nm P4s weren't exactly cool either. Besides like I said, if there was anything to worry about, AMD could have simply grinded another 11um away. At 1G, a 25nm 300mm wafer would just break if only supported at the edge. A 25um 300mm wafer just breaks too easily given the more than 300 operations that need to be done (its even more than that now). The last Turion and Merom bare die look to be about 1mm in thickness with a blue or purple coating. The only time thinner dies are wanted are not for high power but for 3D stacking. If you looked at the Soitec pages, the bulk of the thickness is for wafer handling, 774.9um of it. The other 50nm is the boron doped P silicon layer plus the 50nm oxide layer. Given that, the oxide amorphorus SiO2 layer would roughly equal to 5um of undoped Si. With crystalline SiO2 where the thermal conductivity is 'c \|\| = 0.1143 Wcm-1K-1' or about 13 times lower than bulk silicon, that effective thickness reduces to 650nm. 700nm is what of 775um? Less than 0.1% which is what I claimed. Even the 100um used in 3D stacking would still yield a 0.7% thermal resistance increase for the bare die. After you add in that of the 25um coating, the IHS die interface, the IHS itself, the IHS HSF interface, the HSF itself and the HSF air interface, the additional resistance is miniscule. impex-hightech.de Perhaps you were thinking of zero G processing with that 25nm 300mm wafer? There certainly not enough silicon for even the top layer given 300+ processing steps. Pete