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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Sarmad Y. Hermiz who wrote (228839)	3/24/2007 8:27:11 PM
From: muzosi	Read Replies (1) \| Respond to of 275872

probably the latter. the speed of a synchronous ic is limited by the total gate (let's say a nand2 made of 2 pmos & 2 nmos transistors) delay between two flops. obviously the switching speed of transistors is a component here but also how many levels of gates the designers put in is also very important. in addition to this what type of transistors one uses enters the picture too (high vt vs low vt). if one wants to implement a known function (say x86 decoding, datapath or out of order scheduling) the design space is very large in the sense number of fo4 gates one uses in a single pipeline stage vs the complexity of increasing the pipeline control vs the penalty of having a certain pipeline size on missing branch etc. all of these decisions decide how fast you can run the pipelines, how much power (both dynamic and leakage) you're going to consume and what your yield will be (based on die size).