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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: eetnoyer who wrote (230076)	4/16/2007 11:54:57 AM
From: combjelly	Read Replies (2) \| Respond to of 275872

"It seems as though Intel has placed their bet on EUV making it in time for 22nm, while AMD has taken the other side of it." Good summary of the situation. However, I don't think you got the conclusion right. As smooth often does, he doesn't recognize, I'll let others draw their conclusions as to why, that AMD and Intel have different constraints. And Intel makes the best choices for them, and IBM/AMD optimizes for their situation. Intel had to go with very precise positioning of the mask layers at 90nm. My guess is they were trying to compensate for the power consumption of the P4, but other possibilities exist. So they already had that technology in place, and have built and are building extra fabs to compensate for the lower wafer velocity. With those two things already in hand, double patterning is an obvious choice. AMD, however, is usually capacity constrained. One aspect of APM is to increase wafer velocity by better scheduling. As an AMD spokesman mentioned, they are trying to reduce transit time from 3T to 2T, where T is the ideal minimum time to process a wafer. And they have had some success, just look at how they managed to increase the number of wafers per month at Fab30. So, for AMD, it made more sense to pay a little more to go with immersion instead of developing more precise mask positioning and taking a capacity hit with double patterning. Which probably explains the New York fab. They probably could have ping-ponged back and forth between the two in Dresden, with possibly some expansion with the extra land they have there, but that won't work if they have to face double patterning in a couple of generations. I don't think Intel is gambling on EUV. At this point, they would be foolish to. They just took the most cost effective path for their situation.

To: eetnoyer who wrote (230076)	4/16/2007 1:33:29 PM
From: pgerassi	Read Replies (1) \| Respond to of 275872

Dear Eetnoyer: Double Patterning doesn't get you to 32nm with 65nm tools. You have to go to Quad Patterning at 14 times the steps as immersion requires per 32nm mask. With this you get about 30% of the wafer throughput at much lower yields. A rough estimate that at a given clean room floorspace, it takes between 4 and 5 fabs to do quad patterning as 32nm immersion. And I am not even taking the layout hit due to restrictions on allowable mask patterns (some 32nm masks can not be done with 65nm quad patterning). This will cause quad patterned 32nm dies to be bigger (or less dense) than 32nm immersion dies. Double exposure 45nm dies are bigger than immersion 45nm dies, but not as bad as it will be at 32nm. You see this by the cache size only goes up by 1.5 times for Intel from Conroe to Penryn (4MB -> 6MB) while Barcelona to Shanghai goes up by 2 using all cache L2 and L3 (4x0.5MB+2MB = 4MB -> 4x0.5MB+6MB = 8MB). So by doing this again to get to the 32nm hit, a 32nm Penryn will have 9MB of shared L2 versus a 32nm Shanghai having 4x0.5MB+14MB =16MB. While at 45nm Intel loses its cache advantage, at 32nm Intel falls behind AMD. Boosting the Intel die size to compensate, will require twice the fabs over the hit in throughout and yields. You can see why Intel has to go to ODMC and CSI at 45nm or get really screwed come 32nm. ZRAM would exacerbate this effect. With ZRAM, Shanghai would be at 40.5MB+30MB = 32MB. 32nm Shanghai with ZRAM would be at 40.5MB+70MB = 72MB. A Fusion CPU based on the latter would be like tying a 4GHz DC K10 to a R600 GPU in a 35W TDP laptop. That would give Intel nightmares. Pete