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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: dougSF30 who wrote (231507)	4/25/2007 4:28:34 PM
From: Petz	Read Replies (1) \| Respond to of 275872

Your anti-Christian subtext is outlawed here. I have faith in a person, not in AMD. Message 22527336 From: dougSF30 Read Replies (2) of 231509 With built-in design REDUNDANCY, CACHE banks are an extremely uncommon point of failure. Petz

To: dougSF30 who wrote (231507)	4/25/2007 4:37:16 PM
From: Joe NYC	Read Replies (2) \| Respond to of 275872

Doug, Petz, so your "belief" is that cores can be disabled, but L3 cannot. I think the point Petz is trying to make is that since L3 is goind to be highly redundant, the likelihood of defect in L3 is small. Therefore, there has to be a non-L3 die. Actually, since DCs with L3 are likely to be much smaller volume than non-L3, it is possible that DCs with L3 will come (at least initially), from partially defective QC chips. That way, there would be only 2 types of dies at the beginning of production, QC with L3 and DC without L3. Joe