Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: wbmw who wrote (236940)	7/24/2007 11:04:38 AM
From: j3pflynn	Read Replies (2) \| Respond to of 275872

wbmw, romus - I doubt they've got it right re: TSMC and Fusion. It seems far more likely to me, since Fusion is supposed to start out as a 2 die package, that TSMC could make the GPU die, which would be bulk silicon, while the CPU would continue to be SOI.

To: wbmw who wrote (236940)	7/24/2007 11:27:07 AM
From: Dan3	Read Replies (3) \| Respond to of 275872

Re: TSMC has stated that they won't be running test runs for 45nm until the end of the year. What? They've been targeting production - not just sampling, for this quarter since last year: TSMC plans to start by releasing a low-power version of its 45-nm process, followed by separate general-purpose and high-speed derivatives. Originally, the company had planned to move into "risk production" for its low-power 45-nm technology in next year's fourth quarter. Now, it has pulled in its introduction date and intends to move into risk production in the third quarter of 2007, said Shang-Yi Chiang, senior vice president of research and development at TSMC. eetimes.com And an update: Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) today announced that it would complete 45nm technology qualification and enter production as early as September 2007. The new 45nm process combines the most advanced 193nm immersion photolithography, competitive performance-enhancing silicon strains, and extreme low-k (ELK) inter-metal dielectric material. tsmc.com If they're going to be in production of parts for their customers this quarter, it would be surprising if there weren't samples starting to make it to those customers around now.

To: wbmw who wrote (236940)	7/24/2007 11:48:08 AM
From: romus	Read Replies (1) \| Respond to of 275872

But I think the article has a few things wrong. For one thing, TSMC has stated that they won't be running test runs for 45nm until the end of the year. Dan3 has provided you with 2 links. Here is an additional one: fabtech.org TSMC has said that it expects to start production wafers on its 45nm low-power process platform in September this year. General purpose and high-performance platforms are expected to follow shortly after, TSMC said. A low-power triple gate oxide option is also being offered by the foundry. "Customers expect both performance and reliability from TSMC, a fact that has guided the development of our 45nm process every step of the way," said Dr. Rick Tsai, president and CEO of TSMC. "With our 45nm solution ready and production to be started in September, TSMC provides next-generation technology at the earliest possible time." Key to TSMC's ability to match Intel's plans to migrate to the 45nm node before the end of the year is the continued use of strain-engineering techniques and a second generation low-k dielectric for interconnects dubbed ‘extreme low-k' (ELK) by TSMC. TSMC has not adopted a high-k dielectric or metal gates at the 45nm, making qualification easier and processes less complicated. Previously, TSMC would lag major chip manufacturers' technology node migrations by approximately 12 months, but it would seem that at the 45nm node TSMC has significantly closed the gap, albeit with a less advanced process compared to Intel or AMD and IBM, which use SOI wafers and strain-engineering techniques. TSMC is still committed to bulk CMOS at the 45nm node. As expected, TSMC will use 193nm ArF immersion lithography for the first time across process platforms starting at the 45nm node. ASML is TSMC's sole supplier of DUV lithography tools. TSMC's first 45nm ‘CyberShuttle' has produced working die, according to the company, with a double-digit number of companies in various stages of CyberShuttle testing. "Our customers' enthusiasm for the 45nm CyberShuttle is an auspicious leading indicator of the success of TSMC's 45nm process," said Dr. Rick Tsai, president and CEO of TSMC. "We are marshalling the full resources of our design ecosystem to support our 45nm process and respond to the anticipated demand." TSMC also said that a full range of design support services for its 45nm process were now in place and further CyberShuttles were arranged for May, August and December. May be Digi got JPM's report wrong. I haven't seen this report. Let's hope the issue will be clarified this Thursday.