Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (237466)	7/27/2007 3:48:48 PM
From: dougSF30	Read Replies (2) \| Respond to of 275872

That's not how that calculator is used. Besides, Elmer, who is an expert in the area, said that 0.5 is terrible, and Intel is below .25 for comparison.

To: Petz who wrote (237466)	7/27/2007 11:04:13 PM
From: wbmw	Respond to of 275872

Re: L2+L3 takes 1/3 of the die area xtremesystems.org so the die area susceptible to single defect failure is 189mm. Using .0045 defect density, we get a yield of 0.453581617 Not sure I believe your screwy math. Just because there is cache redundancy, doesn't mean that it is entirely immune from defects. For one thing, you don't treat defects as point problems with zero physical area. Plenty of different defects can ruin a cache in spite of redundancy. 46% would be ideal case, and 32% is worst case. Let's at least agree it will be between this. I wouldn't pretend to know the exact number, but either way, the actual defect density is below industry norms, and it does have an impact on production, cost, and volumes. Re: Hmmm, and I predicted 46%! What can I say? You are totally good, Petz.