Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (237481)	7/27/2007 8:34:49 PM
From: misen	Read Replies (1) \| Respond to of 275872

Petz, cache redundancy does not fix all defects that occur in the cache. Also, with cache generally being denser than random logic, it is more susceptible to the presence of defects that are "killer" defects. So, depending on the redundancy scheme, caches can be either higher-yielding or lower-yield than random logic areas. In general, to get more benefit from redundancy, you need to use more die area for the redundant cache portions. So there is usually a defect-density trade-off decision made early in the design process as to how much redundancy to include (which assumes the process will be at a certain defect density). If you "guess" wrong on the defect density, you will either have a die size that is too large with unused redundancy or low yields due to not enough redundancy. But in any case, you cannot just subtract the cache area from the die size and then plug the resulting die size into a yield calculator (well, you can, but the results are wrong). Misen