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To: wbmw who wrote (238891)	8/16/2007 8:07:53 AM
From: combjelly	Read Replies (1) \| Respond to of 275872

"Now, CJ, I don't make the same gross and inaccurate assumptions about you." BS wanna. You are assuming I know nothing. You are wrong. "I'm just stating the engineering realities as I see them, and from direct experience." Ok. What in your experience, leads you to believe the RTL, presumably in the core, although you were non-specific, would have to be changed due to a change in something connected to the crossbar? Or, for that matter, why anything in the core, other that what I specified, would have to be changed? You threw out a lot of buzz words and did an appeal to authority and proceeded to put me down when I didn't knuckle under. Try making an honest argument. "and set an example of not making posts that have zero content, and are only targeted at discrediting other posters." Projection, wanna. Your post was zero content in that you presented Joe with a straw man argument. No where did I indicate that I thought the L3 consisted solely of the actual cache cells. That was totally gratuitous and inaccurate. Here and on other boards, you seem to labor under the impression that you burnish your reputation by putting others down. You don't. My post about you spinning smoke and insults was accurate, you made a laundry list of assertions and, when asked to back them up, proceeded to sling insults and spin like a top. "The Us versus Them mentality that people like you drive on this forum does not lead to healthy discussion." Glad you recognize it. Now, stop with the Us versus Them and engage in an intellectually honest discussion. If you can.

To: wbmw who wrote (238891)	8/16/2007 3:50:01 PM
From: Petz	Read Replies (1) \| Respond to of 275872

Why don't you follow your own advice instead of hurling another insult at cj? Does the entire core have to be redesigned everytime the HT spec is extended, or if the memory controller external interface is changed? The answer is no, the K8 core was changed very little to accomodate DDR2 vs. DDR and to support HT 2.0 vs. HT 1.0. As with anything isolated by the crossbar. Your "any engineer knows" is just a bunch of hot air. EDIT - I see you've backed down from your "core" assertions a bit. One thing you seem to have forgotten is that AMD already told us the L3 is designed to handle more address bits. Petz