Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: combjelly who wrote (238896)	8/16/2007 12:29:52 PM
From: wbmw	Read Replies (4) \| Respond to of 275872

Re: Ok. What in your experience, leads you to believe the RTL, presumably in the core, although you were non-specific, would have to be changed due to a change in something connected to the crossbar? Or, for that matter, why anything in the core, other that what I specified, would have to be changed? You are making me repeat myself. I have already said that there needn't be any direct changes to the core. However, that doesn't mean the core doesn't need to be revalidated with a cache hierarchy change that may give it different timings, and may require tweaks to the fetch state machine. You are assuming the same basic micro-architecture for the cache controller, but I don't take that for granted, either. It may very well require that Z-RAM needs a brand new pipeline to prevent performance degradation, and that intuitively makes sense, when you realize that address generation is limited by the number of bits in the address, which gets larger as the cache grows bigger. As for changes in the RTL, even if the cores stay absolutely pristine, you will still have your brand new top level RTL code (which rolls up the cache design changes with the rest of the design), and then either has to be re-synthesized, or laid out again using whatever custom design tools the back-end guys have at their disposal. This all takes manpower and time, both of which I claimed in my original response, which was that it might not be worth AMD's while to staff a design team to redesign Shanghai with Z-RAM memory before Sandtiger. Those designers would be much more useful on other future projects. Now, if you consider it "smoke" and "FUD" to make the simple conclusion that AMD should use their designers effectively, then gee... you're a pretty sensitive skeptic, I guess. Just be nice and try not to encourage that behavior across your forum....