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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?


To: wbmw who wrote (238932)8/16/2007 3:24:11 PM
From: Joe NYCRead Replies (1) | Respond to of 275872
 
wbmw,

Just to spell it out for everyone, Z-RAM in an existing design would most likely require:

- New cache cell design (at the very least!)


Of course

- Likely process tweaks or modifications

The claim is that it is minimal

- Reliability verification, additional parity or hardened latches may be required on an unproven design

That may be ongoing as we speak, in test chips. This is where the hang-up is currently, IMO.

- Performance simulation to determine best size and design parameters

That's not really a big deal, IMO. Caches have been around for decades, and the issues are pretty much settled. Additionally, L3 in Barcelona is a complete black box, its effects easily simulated. Well, easily compared to other challenges in core, memory controller, crossbar design.

...-- and quite possible necessitate additional steppings to iterate on the design and fix bugs on a technology that has not yet been proven in any AMD design before it.

First of all, I don't know the first thing about designing microprocessors, but it seems to me that a logical way to go about this is to build test modules (standalone, without processor) and fiddling with that. As I said, it is a black box, so the issuing requests / testing results and timing them, testing reliability should not be all that difficult to test.

This is, IMO, what AMD is doing currently, and it is kind of like inventing a wheel, since nobody has any experience with this technology, AMD is doing it first, which is why it is taking a while,

Joe



To: wbmw who wrote (238932)8/16/2007 3:42:22 PM
From: combjellyRead Replies (1) | Respond to of 275872
 
"Taken altogether, this is a heavy modification of the design and requires a lot of additional work."

Thank you for finally stating your position instead of just handwaving. We could have saved a lot of bandwidth if you had only done this when first asked.



To: wbmw who wrote (238932)8/21/2007 1:45:32 PM
From: TimFRead Replies (1) | Respond to of 275872
 
- New micro-architecture for the cache controller (to compensate for different read and write timings, which are vastly different than SRAM)

Why? LV3 is off of the cross bar, wouldn't it work like any other LV3, or main memory, or access from other processors, its just a request over the crossbar that comes back quicker than a main memory request (but slower than a SRAM LV3 request).