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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (239536)	8/29/2007 1:31:18 PM
From: graphicsguru	Read Replies (2) \| Respond to of 275872

Understand that CSI is "speculative cache coherency." It's game changing. I don't know if anyone has ever tried anything like this before. Certainly not in the x86 space. What Intel is doing is going ahead and using a cache line before knowing absolutely for sure that using it does not create the possibility of an incorrect result. In the rare instance where there turns out to be a problem, they have to back up. The result is much better latency at the cost of much greater complexity. I believe that AMD has been right for these many years. "It's all about latency." Somehow, Intel has managed to make C2D perform better than AMD's parts by a combination of better core design, larger caches and better process parameters. All of this in spite of worse latency. But now, latency is going to turn into an Intel advantage. When that happens, look out.

To: Tenchusatsu who wrote (239536)	8/29/2007 2:05:07 PM
From: Petz	Read Replies (1) \| Respond to of 275872

An Intel presentation about server platforms: download.intel.com Gives some insight into necessity for CSI, and into the Caneland (4S) platform. Basically conclusion is that memory bandwidth and latency are the key drivers for platform performance. Comparing charts 16 and 18, the 4S Caneland platform has the same number of FBDIMM channels as 2S. Four channels of DDR2-667 according to this: physorg.com Seeing as there are several charts in that Intel presentation that point out the bandwidth sensitivity of SPECint_rate, SPECfp_rate and several server benchmarks, I would say that Caneland will be at a distinct disadvantage to 4S Barcelona with 2-3 times the bandwidth. Petz