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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: graphicsguru who wrote (239537)	8/29/2007 2:05:57 PM
From: fastpathguru	Read Replies (2) \| Respond to of 275872

The result is much* better latency at the cost of much greater complexity.* Maybe it's not SO bad... The overall requirements would be: Save the state of the program at the moment the speculative read is "filled" and used (equivalent to an "onboard context switch", worst case), and prevent any potentially tainted results from leaking back out before the cache line is "validated." The "context save" will just suck up processor cycles that would otherwise be waiting for the read to fill anyways. "Rollback" consists of simply "context switching" back, and restarting with the by-now-correctly-filled cache line and read results. Not so crazy. fpg

To: graphicsguru who wrote (239537)	8/29/2007 2:18:08 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 275872

GG, > Understand that CSI is "speculative cache coherency." It's game changing. Huh? That's up to the requesting processor, NOT its bus cluster. If the core wants to speculatively use a cacheline before it is fully snooped, that's up to the core. If the snoop turns out not to be clean, then it's up to the core to undo everything it speculatively executed. That is independent of CSI. > I believe that AMD has been right for these many years. "It's all about latency." It's not like Intel didn't know this. Ever since the Rambus fiasco, Intel has learned about the importance of latency. Hence the need for large caches on Intel processors, for instance. The best way to reduce latency is not to go outside the processor in the first place. Tenchusatsu