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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Saturn V who wrote (241488)	9/29/2007 5:42:56 PM
From: chipguy	Read Replies (1) \| Respond to of 275872

Is greater scalability an intrinsic advantage of the IA 64 architecture ? There is nothing intrinsically special about any 64 bit instruction set architecture. They all can do basic 64 bit integer computation, address 64 bit logical address spaces etc. Differences arise in the performance/cost/power trade-off characteristics of physical implementations and the way they interact with software (programming toolchains, apps, OSes, middleware etc). IPF has most of the intrinsic advantages of RISC ISAs plus the advantage of multiple explicit information channels to allow software to communicate code hints to hardware beyond that available to intrinsically serial ISAs, i.e. all non-EPIC ISAs. This allows highly superscalar MPUs to be built without all the complex, bug prone, and power intensive control logic needed to tease out and utilize information about ILP from a traditional CISC or RISC code stream with serial semantics and rely less on blind speculation by hardware. The trade-off for this is lower code density and and a need for sophisticated compiler technology. IMO EPIC (IPF) does have a small intrinsic advantage over CISC and RISC because of this. A small advantage that grows more important over time because semi process technology increasingly favours using transistors for memory (cache) instead of leaky, high complexity/fan-on/fan-out control logic like parallel variable length instruction decoders and OOO issue queues (an aggressively OOOE processor can easily burn 30% or more of its power budget there alone). That being said, differences in implementation effort, process technology, software quality etc can easily overwhelm ISA effects (x86 would have been dead a decade ago if it couldn't). The real acid test will come when IPF and x86 server MPUs designed by teams given similar resources are made in the same process technology and reach the market at the same time. That will reportedly happen around 2010 or 2011 at 32 nm. BTW, Intel's substantial ramping up of development effort for IPF over the past 18 months and the large absolute size of this effort relative to the small portion of revenue IPF currently represents is a pretty strong indication of how Intel views the advantages of IPF vs x86 going forward to attack RISC and zSeries in the remaining portion of the server processor market it doesn't yet own. This ramp also occurred at a time in which Intel was cutting back costs and jettisoning non-x86 activities such as Xscale and flash. Or is it due to a market segmentation attempt by Intel ? If so, that will give an opening for AMD to exploit. Some of it is segmentation simply from the fact that IPF processors have die size and system level cost budgets well beyond what is feasible for nearly all x86 product segments. IPF designers also do not have to worry about supporting configurations cheap enough for the desktop market or low power enough for mobile. A few years ago AMD exploited weakness in Intel's x86 MPU product lineup to gain share. But at the same time IPF was getting firmly established in mid to high end servers with a software based growing from 500 apps to over 12,500 apps today and growing server sales from nearly a $100m a year to nearly $100m a week. Intel's IPF strategy only benefits AMD to the extent that it might have taken Intel's eye off the ball in terms of keeping its x86 offerings fresh, something that is clearly not happening any longer. OTOH Intel's IPF strategy hurts AMD to the extent that it competes with its server processors along the fringes and could set up a situation of providing enough steady and high margin revenue to allow Intel to Celeronize the x86 server MPU market.