Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Spansion Inc. -- Ignore unavailable to you. Want to Upgrade?

To: Pam who wrote (2939)	1/5/2008 10:45:24 AM
From: Rink	Read Replies (4) \| Respond to of 4590

Pam, Here's some more data about cell sizes / yields / throughput. Some tidbits I collected over time + some as a result of our current discussion. Berkeley paper with cell sizes of various memory models mentions 4F2 and 10F2 cell sizes for NAND and NOR, single level, see slides 32 and 37: bwrc.eecs.berkeley.edu So Mirrorbit Quadbit (4b/c) and NAND MLC (2b/c) would indeed have more or less similar cell sizes. NOR 1b/c old tech was 10F2, Mirrorbit Quadbit 4b/c would be ~2.5F2, close to 2b/c MLC NAND ~2F2. Basically this normally would mean you are right on cell size. Still: From 3/1/'08: Due to the increased storage capacity per cell, MirrorBit Quad technology is capable of delivering up to 30 percent smaller effective cell size per bit than floating-gate MLC NAND Flash memory technology at the same process technology node. investor.spansion.com Basically this indicates that the straight forward reasoning based on data provided by the Berkeley paper is probably not 100% applicable to Mirrorbit. Based on this Spansion statement I guessed in my previous post to you that 65nm Quadbit effective cell size might be comparable with ~50nm MLC NAND (note this is really a guess because I'm very far from being an expert). It however also fits with other tidbits I heared previous years. An old tidbit that would support above notion that Mirrorbit has smaller effective cell size than Strataflash: Back in 2005 Spansion effective cell size for Mirrorbit was mentioned to be 23% better than Intel's Strataflash (obviously a lot changed, but the basic tech didn't so it's not unreasonable to presume this situation didn't change all too much since then)http://www.spansion.com/about/news/articles/spansion_takes_nor_flash_lead.pdf Fornel workshop on nonvolatile memory concepts below 50nm (an absolute data gem this is). Mentions multi bit charge trapping (like mirrorbit) at 6F2 cell size, 3F2 bit size, based on single level charges (2 single level, separate charges per cell). This is some 25% below single level NAND. So Spansion's statement of 30% lower effective cell size for Quadbit (MLC Mirrorbit) than MLC NAND is not out of reach. From march 2007. Page 14: fornel.de. So my conclusion obviously is that the straight forward reasoning based on the earlier mentioned data from the Berkeley paper might possibly be applicable to MLC floating gate but likely not to Mirrorbit. Next there are other aspects to consider as well (yields and throughput): Spansion claimed intrinsic yields of Mirrorbit technology 30% higher than comparable floating gate NOR back in 2004 (again a lot changed since then but the fundamental technology didn't so it's imo not unreasonable to presume this figure has changed dramatically). spansion.com Elsewhere Spansion stated several times 40% less process steps for Mirrorbit compared to floating gate NOR which leads to significantly higher throughput using rather similar equipment. The above + the absence of 300mm NOR fabs for Numonyx were btw the reasons for my earlier conclusion that Numonyx is bound to shrink next year, and after that too if it doesn't work miracles with phase change soon enough. Both Spansion and Samsung should be able to gain share mainly from them for at least next year and reasonably probably beyond that too. Obviously this is also the basis for my earlier statement that Spansion might become the only more or less pure traditional NOR player to come out of the transition to newer technologies in possibly a good shape. With Mirrorbit, ORNAND, Quadbit, Eclipse, HD-SIM, possible SONOS (they've got a good basis of technology to get there), 300mm fabs, TSMC and SMIC as partners in different area's, no competition with customers (like Samsung), a good roadmap to 45nm, they have imo a reasonable basis to do even well in a not too refreshing pure NOR market. Regards, Rink Some additional data just for future ref: Some more gleaned from the Fornel workshop on nonvolatile memory concepts below 50nm mentioned earlier. - It mentions charge trapping vs floating gate, plus SONOS both Spansion, Samsung, and Macronix/Qimonda (BE-SONOS) concepts, and phase change (PCM). - It mentions quite reasonable scaling for charge trapping NOR(like mirrorbit) down to 50nm with <3F2 bit size, and down to 35/40nm with <4F2 bit size (p18). fornel.de Intel 65nm Strataflash 1Gb: 19Mb/mm2, 0.045um2 cell size, 0.023um2 bit size, 10.7F2 (not ideal scaling btw, this reduced scaling for floating gate is imo set to get worse below 65nm) Intel 90nm Strataflash 512Mb: 11.6Mb/mm2, 0.076um2 cell, 0.038 bit, 9.4F2 STM 65nm Strataflash: ~20Mb/, ~0.042um^2 cell size. Spansion 90nm Mirrorbit: ~12Mb/, ~0.070um^2 cell size. See p13 from above mentioned fornel presentation: fornel.de i.cmpnet.com Intel/IMFT also at 4F2 cell size for 50nm NAND, from 9/18/'06: audiodesignline.com

To: Pam who wrote (2939)	1/6/2008 4:15:06 AM
From: Woerns	Read Replies (1) \| Respond to of 4590

@PAM Thanks for enriching our discussion! SPSN says its NVM does not compete with NAND but rather with DRAM. The eclipse MCP is supposed to reduce the amount of embedded DRAM or possibly not needing any DRAM at all (in an optimistic case, basically we don't know if it's possible). In addition to reducing the costs of the MCP (at least if the amount of needed storage is not too big) the topic of power consumption comes into play. I don't have a link but I heard that several manufactures are working on handsets fed with normal batteries instead of rechargeable batteries. (IMO an environment killer btw since nearly 100% of batteries end in the garbage dump instead of being cleaned up regularly.) These mobile phones are supposed to be low-end for the emerging markets so there won't be any need for large NAND amounts to store data. But a low power consumption of the whole device is essential, IMO it is the market enabler. Regards