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Technology Stocks : Spansion Inc. -- Ignore unavailable to you. Want to Upgrade?

To: Rink who wrote (2946)	1/5/2008 1:11:08 PM
From: Rink	Respond to of 4590

Just to add to the prev post here's a white paper from Spansion from around the time the first gen 90nm Mirrorbit Quad was sampled, I think it's from H2/'06. It contains an effective cell size estimates diagram on page 5 dated Sept '06. Spansion's estimates are more or less in line with most other data and estimates mentioned earlier. 65nm Mirrorbit Quad was estimated approx as dense as 55nm MLC NAND, or 65nm Mirrorbit Quad was estimated to be some 20-30% denser than 65nm MLC NAND. spansion.com Regards, Rink

To: Rink who wrote (2946)	1/6/2008 8:54:08 PM
From: Pam	Read Replies (1) \| Respond to of 4590

So Mirrorbit Quadbit (4b/c) and NAND MLC (2b/c) would indeed have more or less similar cell sizes. NOR 1b/c old tech was 10F2, Mirrorbit Quadbit 4b/c would be ~2.5F2, close to 2b/c MLC NAND ~2F2. Basically this normally would mean you are right on cell size. In a highly competitive environment, such as NAND, the difference of 0.5f^2 in cell size is huge, especially when you are dealing with high densities like 16Gb, 32Gb and 64Gb's! Spansion's highest density for ORNAND is just 4Gb! Do you know if it is a monolithic chip or a dual-die or a quad-die? Still: From 3/1/'08: Due to the increased storage capacity per cell, MirrorBit Quad technology is capable of delivering up to 30 percent smaller effective cell size per bit than floating-gate MLC NAND Flash memory technology at the same process technology node. Basically this indicates that the straight forward reasoning based on data provided by the Berkeley paper is probably not 100% applicable to Mirrorbit. Exactly. As I said in my earlier post, if you are going to look at cell size, they have to be at the same node and if you are going to compare products from different nodes, make sure you are comparing die size for identical capacity chips. You have to look at other things also, but let's just ignore them and keep it simple. Based on this Spansion statement I guessed in my previous post to you that 65nm Quadbit effective cell size might be comparable with ~50nm MLC NAND (note this is really a guess because I'm very far from being an expert). It however also fits with other tidbits I heared previous years. Well, you would be fairly close if you had compared 65nm Quadbit with 56nm NAND MLC (instead of 50nm) but you also have to consider that Toshiba/Sandisk are done with their successful transition to 56nm and are now moving to 43nm and Spansion is sampling 65nm, so they are about 2 nodes behind and that is huge in semiconductor business! Fornel workshop on nonvolatile memory concepts below 50nm (an absolute data gem this is). Mentions multi bit charge trapping (like mirrorbit) at 6F2 cell size, 3F2 bit size, based on single level charges (2 single level, separate charges per cell). This is some 25% below single level NAND. So Spansion's statement of 30% lower effective cell size for Quadbit (MLC Mirrorbit) than MLC NAND is not out of reach. Based on the chart provided by Spansion, and assuming it is accurate, it would seem so. But then as I said, Spansion is behind and pretty soon they will fall further behind as Toshiba/Sandisk introduce 3 b/c first at 56nm, and then at 43nm. Every node and every transition is extremely important. If you do the math, 2 b/c NAND at 43nm is cheaper than 3 b/c NAND at 56nm so they are inclined to do 43nm first but they will also do 3 b/c at 56nm despite the cost disadvantage to get their hands dirty with new technology at a more mature node, which is generally easier. I also believe, Spansion's Quadbit ORNAND products have inferior Write speeds and endurance compared to MLC NAND. Next there are other aspects to consider as well (yields and throughput): Spansion claimed intrinsic yields of Mirrorbit technology 30% higher than comparable floating gate NOR back in 2004 (again a lot changed since then but the fundamental technology didn't so it's imo not unreasonable to presume this figure has changed dramatically). Both, yields and throughput are important. Toshiba/Sandisk generally haven't had any problems with their yields and are pretty efficient, lowest-cost producers. I am not familiar with yields for Spansion but Toshiba's run at high 90's! Thanks to ECC which makes even dies with errors economically useful as lower density dies! Elsewhere Spansion stated several times 40% less process steps for Mirrorbit compared to floating gate NOR which leads to significantly higher throughput using rather similar equipment. Do you know approximately how much time it takes for Spansion's ORNAND to be manufactured from start to a finish? Just to add to the prev post here's a white paper from Spansion from around the time the first gen 90nm Mirrorbit Quad was sampled, I think it's from H2/'06. It contains an effective cell size estimates diagram on page 5 dated Sept '06. Spansion's estimates are more or less in line with most other data and estimates mentioned earlier. 65nm Mirrorbit Quad was estimated approx as dense as 55nm MLC NAND, or 65nm Mirrorbit Quad was estimated to be some 20-30% denser than 65nm MLC NAND. As I indicated earlier, it will be really hard for Spansion to catch-up in data storage. NAND players are moving extremely fast and they have the resources. Toshiba/Sandisk are about to start 3 b/c at 56nm in the coming months, so I modified the chart a bit to see what it would look like. The red line at the bottom is added by me for 3 b/c starting 56nm.

To: Rink who wrote (2946)	1/7/2008 5:46:31 PM
From: mlc178	Read Replies (1) \| Respond to of 4590

Quad bit MirrorBit and MLC NAND don't play in the same arena at present. Quad bit Mirrorbit is only being used to store books, movies,... That is, mostly read-only for low reliability and/or low performance applications. Not saying its characteristic won't improve in the future, but at present its market is limited to content delivery. Spansion has some work cut out to bring QB Mirrorbit for use in diverse applications.

To: Rink who wrote (2946)	2/18/2008 6:01:47 AM
From: Rink	Read Replies (1) \| Respond to of 4590

Paper on NAND replacement technologies: ewh.ieee.org From EDS, apr '07. Contains good technical info, especially as of slide 34. Conclusion is that floating gate (both NAND and NOR) won't survive the decade. For NAND it's going to be replaced by technologies like 3D-flash and TANOS (both based on SONOS; Tosh is working on 3D SONOS, and Samsung has TANOS which is a metal gate high-k SONOS). For NOR it might be replaced by a technology like PCM. Study doesn't include NROM based Quadbit, or newer NROM based 2b/c SONOS announced as ORNAND2. Spansion's SONOS looks to be twice as dense to me btw. It's clear though that about the whole industry is heading towards SONOS-like technology and charge trapping to overcome scaling problems of floating gate. - Samsung might be ahead of Spansion for as far as new material usage is concerned (metal gate, high-k). - Toshiba might be ahead of Spansion using 3D SONOS flash structures. - Both those are however targeted at 32nm or possibly even below as both Samsung and Tosh are pushing floating gate till the extreme limits, while Spansion has been producing SONOS related structures for years and is evolving it (quadbit, ornand2) I wouldn't mind some si-engineer looking over this paper (link above) and the Fornel workshop presentation I used earlier that also contains good detail: fornel.de , as well as the eetimes articles referenced here: Message 24178269 EDIT: Here's a recent SONOS patent assigned to Samsung: freepatentsonline.com It might show 2b/c SONOS. Regards, Rink PS, Quite silly those fellows responsible for this paper ;-)