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To: chipguy who wrote (248606)3/11/2008 11:02:00 AM
From: pgerassiRead Replies (2) | Respond to of 275872
 
Chipguy:

Mas stated that Intel fuses off dies to get SC and lower cache variants. And that is most definitely true. You just have to acknowledge that all 512KB and 3MB L2 C2D variants must be fused off cache and/or cores, period! Trying to turn around his statements to push the myth that Intel doesn't do so, is just a swarmy way of acknowledging that Wbmw's statement doesn't have any legs to stand on.

There are four known 65nm dies, a SC variant with no L2 cache (I haven't seen this sold anywhere), a SC variant with 1MB L2, a DC variant with 2MB L2 and a DC variant with 4MB of L2. There is now a 45nm DC 6MB L2 variant which fuses off to 3MB L2.

Pete