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To: chipguy who wrote (248640)	3/11/2008 10:20:11 PM
From: Elmer Phud	Respond to of 275872

LOL, so you think Intel saws the die of defective dual core C2Ds in half to make single core chips like the Celeron 200? :-P <G>

To: chipguy who wrote (248640)	3/12/2008 12:10:02 AM
From: pgerassi	Read Replies (1) \| Respond to of 275872

Chipguy: Funny you should use that document and not read it (as you accused me of doing to one of your posts low on facts). Its at least a SC 1MB L2 die, but only 512KB of the L2 are active. It plainly states that on chapter 1 (page 9 from the beginning per Adobe Reader) paragraph 5, in the thermal specifications and others. The given die size is 11.1mm times 8.2mm or 91.02mm2, far too big to be a SC with just 512KB of cache. Even bigger than a 80.66mm2 SC 1MB L2 die. Every one of these is a fused die. And the document does state typical sizes. There is enough room for a dual core die to be used (12.6 by 12.8mm or 161mm2) fused to be one core and 1/4 the L2 cache. The DC 2MB die being 103mm2 and the SC 1MB die being 80.66mm2. The given die size is almost the geometric mean between the two die sizes. Thus all of the dies are fused and a good deal of them may even be fused from DC 2MB dies. Kind of shoots a big gaping hole in your theories. But you would have known that if you would read all of the document rather than the part you needed. Pete

To: chipguy who wrote (248640)	3/12/2008 2:15:19 AM
From: THE WATSONYOUTH	Respond to of 275872

Have a look at the package mechanical specifications, especially C1 and C2, for the Celeron 200 here: We're talking about the 400 series as if you didn't know. What are the die dimensions inside the package for the 400 series? Why was it not specified as in the 200 series case.? Are you saying that a 143mm^2 or 111mm^2 die would not fit in that package? Unless you can prove that they could not fit, then I think it is clear that they fit very well........to the tune of over 10 million per quarter. THE WATSONYOUTH