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To: chipguy who wrote (248669)	3/12/2008 3:10:43 PM
From: pgerassi	Read Replies (2) \| Respond to of 275872

Chipguy: You don't know what you are talking about. The passivity coating BS is just one such example. It is not very thick. Well under 50um. Not enough to change the size of a die measured in 0.1mm units. Wbmw's link to the Celeron 500 series clearly shows that passivity coatings don't affect the die sizes as the area works out exactly to the die sizes reported by many sources. I have designed memory in the old days where every transistor was precious. Those days are long gone. However I did find a redundant column scheme for Power6 CPUs by IBM going into great detail: research.ibm.com It has 16 spare rows per 256 line array, but just two columns spare in each 72 bit wide array in the 16KB L1D cache macro. IBM's designers allow for up to 6 repairs (each spare can't replace any object, just some of them) for this macro. However an error in the critical decode, control or I/O circuits or just too many errors still requires the fuse off of the section of which there are 4 in Power6's L1D cache. And that happens a lot, more than you are willing to admit. Still it shows that column spares are more rare than row ones given that there are 16 row spares (1/16th), but only 2 for columns (1/36th). And there are other macros for all of the caches, directories and TLBs on that die. IBM Power6 is a large chip and can easily have more than one defect in a particular die. Yet the dumb statement about passivity coatings altering die sizes by more than 10% rapidly reduces your credibility. It just goes to show that expertise in one tiny area, doesn't extend to others. Pete