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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: pgerassi who wrote (248677)	3/12/2008 3:28:26 PM
From: chipguy	Read Replies (1) \| Respond to of 275872

It has 16 spare rows per 256 line array, but just two columns spare in each 72 bit wide array LOL, I guess this an example of one of those "rare" designs with both row and column redundancy. And it's a 16 KB first level cache array macro no less. No doubt as you get into the hundreds of KB and megabyte range and start occupying some serious die area having both row and column redundancy becomes even rarer. :-P

To: pgerassi who wrote (248677)	3/12/2008 3:56:42 PM
From: wbmw	Read Replies (1) \| Respond to of 275872

Re: You don't know what you are talking about. The passivity coating BS is just one such example. It is not very thick. Well under 50um. Not enough to change the size of a die measured in 0.1mm units. Wbmw's link to the Celeron 500 series clearly shows that passivity coatings don't affect the die sizes as the area works out exactly to the die sizes reported by many sources. The data proves that you are wrong Pete. No other way to explain how the mobile die (without this material) is 81 mm^2, or about 10 mm^2 smaller than the die used in the Celeron 220 (with the material).