SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?


To: Elmer Phud who wrote (252916)6/6/2008 12:18:15 AM
From: pgerassiRead Replies (2) | Respond to of 275872
 
Ephud:

You are forgetting design has a big effect on yields. You can have a low DD and still have bad yields. Look at nVidia's GTX280 GPU. It has a huge die size and even given TSMCs low DD 55nm process, it still will have bad yields.

Besides DD is adjusted for layers, process types and design complexity so as to better compare between fabs across the industry. So the actual yield for a given highly complex process with 200+ masks using DEDP is far lower than the DD number implies. IIRC DD is normalized to 25 mask sets, SESP process and 100mm2 die size. Else it would be difficult to compare a fab making DRAM to one making high performance cutting edge logic.

And the yield I use is for saleable dies per possible dies on a wafer. That takes care of binning, design, packaging and line yields. Intel's 45nm HiK/MG DEDP process has another slowdown with line speed (wafers per month) reductions per M2 in fab cleanroom space. It causes further reductions in saleable dies per quarter.

As to A2 being perfect, I actually said it needed a few more respins. And that it was usual at this stage. For a bad ODMC sample to be used in a preview, it means that Nehalem isn't close to production yet, "near final" is the term I saw used.

Pete