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To: pgerassi who wrote (252920)	6/6/2008 12:50:27 AM
From: Elmer Phud	Read Replies (1) \| Respond to of 275872

You are forgetting design has a big effect on yields. You can have a low DD and still have bad yields. I don't know where you're getting this. It's just not true for a company such as Intel. DD is yield. Design and process are tightly coupled. The process doesn't know what design is being fabed. The defects don't know which design it is. Each product has to use the same design rules. 45nm is healthy so any design fabed on it using standard design rules should see the same DD as any other product. This isn't TSMC or UMC and it certainly isn't IBM. Intel's 45nm HiK/MG DEDP process has another slowdown with line speed (wafers per month) reductions per M2 in fab cleanroom space. It causes further reductions in saleable dies per quarter. Not even close. I suppose you picked this expertise up when you studied Japanese Law.

To: pgerassi who wrote (252920)	6/6/2008 1:27:41 AM
From: misen	Read Replies (1) \| Respond to of 275872

Pete writes: Besides DD is adjusted for layers, process types and design complexity so as to better compare between fabs across the industry. So the actual yield for a given highly complex process with 200+ masks using DEDP is far lower than the DD number implies. IIRC DD is normalized to 25 mask sets, SESP process and 100mm2 die size. Else it would be difficult to compare a fab making DRAM to one making high performance cutting edge logic. Do you really think that any semiconductor process anywhere has 200+ mask layers? Misen