Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Elmer Phud who wrote (252922)	6/6/2008 9:50:39 AM
From: pgerassi	Read Replies (1) \| Respond to of 275872

Ephud: You still don't get it. DD is normalized so as to compare fabs. It doesn't change with the process. A 5ML SESP process is far less complicated than a 11ML DEDP HiK/MG process. Its real DD is normalized to the other so that fabs using either process can be truly compared. Second, if design rules were all that great, Prescott would not have been poor originally. Prescott required a better process to meet its design targets than it had. There have been times that a process's design rules were bad. What was fine in the lab turned out to be bad in production. It took Intel 5 months to get something decent out. And yields that I and many others look at isn't the one that is used by fabrication personnel. Its the one that looks at the whole from design all the way to the shipping dock. Saleable yield looks at binning, process, design, die size, packaging and a few other things. A failure or poor results in any one of them can make the output terrible overall. Heck the fab can do a great job with 90% good working dies from a wafer, but the speeds of the resulting chips may be 1/2 of what is needed to sell. So the overall saleable yield is near zero. Or there could be a design flaw like FDIV where every die is bad. The problem wasn't in the fabrication, but the design. As for the other problem, a DEDP uses so many more steps than one using SESP, that the DD thats normalized from it is even further than one with a SESP. Up until just recently, the differences between Intel's process and AMD's were minor as far as line speed. Their scanners were fairly similar in capabilities. But the tools for 45nm weren't ready when Intel wanted to go to it. They had a choice of waiting for the tools to get ready and being first in line for them or use tricks to existing tools to get a similar result. They did the latter. The thing is those tricks required the wafers to go through a lot more steps than before and some of those steps take much longer as well. And the result is less accurate than using the better tools. Thus they either use more tools to get the same line rates or they have less line rate with the same amount of tools. Given that most fabs are well filled with tools, the second choice is the most likely. And that means that less wafers are processed. This exacerbates the output reductions. Thus with two fabs with world class DDs, one has a higher raw DD because the process is more complicated (more mask sets) than the other and it is also slower than the other to boot. It does have an offset in lower cost scanners though, but likely not enough to cover the lower line yield and the lower line speed. That's ok as long as the resulting dies are more valuable. One other thing, this all started when I remarked that the Nehalem samples are low yielding. If the samples yielded enough good parts, a sample that had a bad ODMC would not have reached OEMs. If the stepping were close to production worthy, that would not have happened especially as Intel tends to cherry pick parts for OEM samples and reviewers. Ergo, the stepping is not yet close to be ready for production. This is normal for an untried new design using a new platform and functionality. I would have been quite surprised, if it didn't take quite a few respins to get it ready for production. Pete